Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for error detection and correction of data transferred between a CPU and system memory

Method and apparatus for error detection and correction of data transferred between a CPU and system memory

US Patent 5455939 · Granted Oct 3, 1995

Estimated economic value: $55,152,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Launching a secure kernel in a multiprocessor system2017
Launching a secure kernel in a multiprocessor system2016
Launching a secure kernel in a multiprocessor system2015
Launching a secure kernel in a multiprocessor system2014
Scalable distributed memory and I/O multiprocessor system2014
Dynamic accelerator reconfiguration via compiler-inserted initialization message2013
Launching a secure kernel in a multiprocessor system2013
Scalable distributed memory and I/O multiprocessor system2012
Launching a secure kernel in a multiprocessor system2012
Launching a secure kernel in a multiprocessor system2012
Method and apparatus for coherent device initialization and access2011
Coherent input output device2011