| 6907487 |
Enhanced highly pipelined bus architecture |
Gurbir Singh, Robert Greiner, Stephen S. Pawlowski, David L. Hill |
2005-06-14 |
| 6880031 |
Snoop phase in a highly pipelined bus architecture |
Gurbir Singh, Robert Greiner, Stephen S. Pawlowski, David L. Hill |
2005-04-12 |
| 6807592 |
Quad pumped bus architecture and protocol |
Gurbir Singh, Robert Greiner, Stephen S. Pawlowski, David L. Hill |
2004-10-19 |
| 6804735 |
Response and data phases in a highly pipelined bus architecture |
Gurbir Singh, Robert Greiner, Stephen S. Pawlowski, David L. Hill |
2004-10-12 |
| 6609171 |
Quad pumped bus architecture and protocol |
Gurbir Singh, Robert Greiner, Stephen S. Pawlowski, David L. Hill |
2003-08-19 |
| 6601121 |
Quad pumped bus architecture and protocol |
Gurbir Singh, Robert Greiner, Stephen S. Pawlowski, David L. Hill |
2003-07-29 |
| 6041403 |
Method and apparatus for generating a microinstruction responsive to the specification of an operand, in addition to a microinstruction based on the opcode, of a macroinstruction |
Darrell D. Boggs, Alan B. Kyker |
2000-03-21 |
| 5822555 |
Method and apparatus for aligning an instruction boundary in variable length macroinstructions with an instruction buffer |
Gary L. Brown |
1998-10-13 |
| 5673427 |
Packing valid micro operations received from a parallel decoder into adjacent locations of an output queue |
Gary L. Brown, Adrian Carbine |
1997-09-30 |
| 5668985 |
Decoder having a split queue system for processing intstructions in a first queue separate from their associated data processed in a second queue |
Adrian Carbine, Gary L. Brown, Bradley D. Hoyt, Rajesh Kumar |
1997-09-16 |
| 5630083 |
Decoder for decoding multiple instructions in parallel |
Adrian Carbine, Gary L. Brown |
1997-05-13 |
| 5600806 |
Method and apparatus for aligning an instruction boundary in variable length macroinstructions with an instruction buffer |
Gary L. Brown |
1997-02-04 |
| 5586277 |
Method for parallel steering of fixed length fields containing a variable length instruction from an instruction buffer to parallel decoders |
Gary L. Brown |
1996-12-17 |
| 5581717 |
Decoding circuit and method providing immediate data for a micro-operation issued from a decoder |
Darrell D. Boggs, Gary L. Brown |
1996-12-03 |
| 5566298 |
Method for state recovery during assist and restart in a decoder having an alias mechanism |
Darrell D. Boggs, Gary L. Brown, Michael M. Hancock, Gail M. Rupnick |
1996-10-15 |
| 5559974 |
Decoder having independently loaded micro-alias and macro-alias registers accessible simultaneously by one micro-operation |
Darrell D. Boggs, Gary L. Brown, Michael M. Hancock |
1996-09-24 |
| 4302908 |
Livestock detaining gate |
— |
1981-12-01 |