| 11372757 |
Tracking repeated reads to guide dynamic selection of cache coherence protocols in processor-based devices |
Kevin N. Magill, Eric F. Robinson, Jason Panavich, Michael B. Mitchell, Michael P. Wilson |
2022-06-28 |
$238,915,000 |
| 11354239 |
Maintaining domain coherence states including domain state no-owned (DSN) in processor-based devices |
Eric F. Robinson, Kevin N. Magill, Jason Panavich, Michael B. Mitchell, Michael P. Wilson |
2022-06-07 |
$255,877,000 |
| 11138114 |
Providing dynamic selection of cache coherence protocols in processor-based devices |
Kevin N. Magill, Eric F. Robinson, Jason Panavich, Michael P. Wilson, Michael B. Mitchell |
2021-10-05 |
$188,794,000 |
| 11093396 |
Enabling atomic memory accesses across coherence granule boundaries in processor-based devices |
Eric F. Robinson, Jason Panavich, Kevin N. Magill, Michael B. Mitchell, Michael P. Wilson |
2021-08-17 |
$196,769,000 |
| 10133670 |
Low overhead hierarchical connectivity of cache coherent agents to a coherent fabric |
Ramadass Nagarajan, Jose Niell, Michael T. Klinglesmith, Ganesh Kumar |
2018-11-20 |
$25,900,000 |
| 8205111 |
Communicating via an in-die interconnect |
David L. Hill, Robert Greiner, Tim Frodsham, Anant Deval, Mark Waggoner |
2012-06-19 |
$20,138,000 |
| 8122194 |
Transaction manager and cache for processing agent |
Chinna Prudvi |
2012-02-21 |
$21,312,000 |
| 7555603 |
Transaction manager and cache for processing agent |
Chinna Prudvi |
2009-06-30 |
$20,585,000 |
| 7487305 |
Prioritized bus request scheduling mechanism for processing devices |
David L. Hill |
2009-02-03 |
$17,091,000 |
| 7143242 |
Dynamic priority external transaction system |
David L. Hill, Chinna Prudvi, Deborah T. Marr |
2006-11-28 |
$16,743,000 |
| 7133981 |
Prioritized bus request scheduling mechanism for processing devices |
David L. Hill |
2006-11-07 |
$13,207,000 |
| 6782457 |
Prioritized bus request scheduling mechanism for processing devices |
David L. Hill |
2004-08-24 |
$22,522,000 |
| 6735675 |
Method and apparatus for altering data length to zero to maintain cache coherency |
Paul Breuder, David L. Hill, Chinna Prudvi |
2004-05-11 |
$33,328,000 |
| 6732242 |
External bus transaction scheduling system |
David L. Hill, Paul Breuder, Robert Greiner |
2004-05-04 |
$23,705,000 |
| 6668309 |
Snoop blocking for cache coherency |
Paul Breuder, Matthew A. Fisch |
2003-12-23 |
$55,491,000 |
| 6654837 |
Dynamic priority external transaction system |
David L. Hill, Chinna Prudvi, Deborah T. Marr |
2003-11-25 |
$50,228,000 |
| 6606692 |
Prioritized bus request scheduling mechanism for processing devices |
David L. Hill |
2003-08-12 |
$56,289,000 |
| 6578116 |
Snoop blocking for cache coherency |
Paul Breuder, Matthew A. Fisch |
2003-06-10 |
$73,878,000 |
| 6578114 |
Method and apparatus for altering data length to zero to maintain cache coherency |
Paul Breuder, David L. Hill, Chinna Prudvi |
2003-06-10 |
$73,878,000 |
| 6499090 |
Prioritized bus request scheduling mechanism for processing devices |
David L. Hill |
2002-12-24 |
$92,784,000 |
| 6460119 |
Snoop blocking for cache coherency |
Paul Breuder, Matthew A. Fisch |
2002-10-01 |
$50,099,000 |
| 6434677 |
Method and apparatus for altering data length to zero to maintain cache coherency |
Paul Breuder, David L. Hill, Chinna Prudvi |
2002-08-13 |
$41,871,000 |
| 6412091 |
Error correction system in a processing agent having minimal delay |
David L. Hill, Chinna Prudvi, Paul Breuder |
2002-06-25 |
$55,737,000 |
| 6401172 |
Recycle mechanism for a processing agent |
Chinna Prudvi, David L. Hill |
2002-06-04 |
$75,138,000 |
| 6378048 |
“SLIME” cache coherency system for agents with multi-layer caches |
Chinna Prudvi, Paul Breuder, Quinn W. Merrill, Harish Kumar, Brent E. Lince |
2002-04-23 |
$65,430,000 |
