Issued Patents All Time
Showing 25 most recent of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11372757 | Tracking repeated reads to guide dynamic selection of cache coherence protocols in processor-based devices | Kevin N. Magill, Eric F. Robinson, Jason Panavich, Michael B. Mitchell, Michael P. Wilson | 2022-06-28 |
| 11354239 | Maintaining domain coherence states including domain state no-owned (DSN) in processor-based devices | Eric F. Robinson, Kevin N. Magill, Jason Panavich, Michael B. Mitchell, Michael P. Wilson | 2022-06-07 |
| 11138114 | Providing dynamic selection of cache coherence protocols in processor-based devices | Kevin N. Magill, Eric F. Robinson, Jason Panavich, Michael P. Wilson, Michael B. Mitchell | 2021-10-05 |
| 11093396 | Enabling atomic memory accesses across coherence granule boundaries in processor-based devices | Eric F. Robinson, Jason Panavich, Kevin N. Magill, Michael B. Mitchell, Michael P. Wilson | 2021-08-17 |
| 10133670 | Low overhead hierarchical connectivity of cache coherent agents to a coherent fabric | Ramadass Nagarajan, Jose Niell, Michael T. Klinglesmith, Ganesh Kumar | 2018-11-20 |
| 8205111 | Communicating via an in-die interconnect | David L. Hill, Robert Greiner, Tim Frodsham, Anant Deval, Mark Waggoner | 2012-06-19 |
| 8122194 | Transaction manager and cache for processing agent | Chinna Prudvi | 2012-02-21 |
| 7555603 | Transaction manager and cache for processing agent | Chinna Prudvi | 2009-06-30 |
| 7487305 | Prioritized bus request scheduling mechanism for processing devices | David L. Hill | 2009-02-03 |
| 7143242 | Dynamic priority external transaction system | David L. Hill, Chinna Prudvi, Deborah T. Marr | 2006-11-28 |
| 7133981 | Prioritized bus request scheduling mechanism for processing devices | David L. Hill | 2006-11-07 |
| 6782457 | Prioritized bus request scheduling mechanism for processing devices | David L. Hill | 2004-08-24 |
| 6735675 | Method and apparatus for altering data length to zero to maintain cache coherency | Paul Breuder, David L. Hill, Chinna Prudvi | 2004-05-11 |
| 6732242 | External bus transaction scheduling system | David L. Hill, Paul Breuder, Robert Greiner | 2004-05-04 |
| 6668309 | Snoop blocking for cache coherency | Paul Breuder, Matthew A. Fisch | 2003-12-23 |
| 6654837 | Dynamic priority external transaction system | David L. Hill, Chinna Prudvi, Deborah T. Marr | 2003-11-25 |
| 6606692 | Prioritized bus request scheduling mechanism for processing devices | David L. Hill | 2003-08-12 |
| 6578116 | Snoop blocking for cache coherency | Paul Breuder, Matthew A. Fisch | 2003-06-10 |
| 6578114 | Method and apparatus for altering data length to zero to maintain cache coherency | Paul Breuder, David L. Hill, Chinna Prudvi | 2003-06-10 |
| 6499090 | Prioritized bus request scheduling mechanism for processing devices | David L. Hill | 2002-12-24 |
| 6460119 | Snoop blocking for cache coherency | Paul Breuder, Matthew A. Fisch | 2002-10-01 |
| 6434677 | Method and apparatus for altering data length to zero to maintain cache coherency | Paul Breuder, David L. Hill, Chinna Prudvi | 2002-08-13 |
| 6412091 | Error correction system in a processing agent having minimal delay | David L. Hill, Chinna Prudvi, Paul Breuder | 2002-06-25 |
| 6401172 | Recycle mechanism for a processing agent | Chinna Prudvi, David L. Hill | 2002-06-04 |
| 6378048 | “SLIME” cache coherency system for agents with multi-layer caches | Chinna Prudvi, Paul Breuder, Quinn W. Merrill, Harish Kumar, Brent E. Lince | 2002-04-23 |