| 6735675 |
Method and apparatus for altering data length to zero to maintain cache coherency |
Derek T. Bachand, David L. Hill, Chinna Prudvi |
2004-05-11 |
| 6732242 |
External bus transaction scheduling system |
David L. Hill, Robert Greiner, Derek T. Bachand |
2004-05-04 |
| 6668309 |
Snoop blocking for cache coherency |
Derek T. Bachand, Matthew A. Fisch |
2003-12-23 |
| 6578114 |
Method and apparatus for altering data length to zero to maintain cache coherency |
Derek T. Bachand, David L. Hill, Chinna Prudvi |
2003-06-10 |
| 6578116 |
Snoop blocking for cache coherency |
Derek T. Bachand, Matthew A. Fisch |
2003-06-10 |
| 6460119 |
Snoop blocking for cache coherency |
Derek T. Bachand, Matthew A. Fisch |
2002-10-01 |
| 6434677 |
Method and apparatus for altering data length to zero to maintain cache coherency |
Derek T. Bachand, David L. Hill, Chinna Prudvi |
2002-08-13 |
| 6412091 |
Error correction system in a processing agent having minimal delay |
David L. Hill, Chinna Prudvi, Derek T. Bachand |
2002-06-25 |
| 6378048 |
“SLIME” cache coherency system for agents with multi-layer caches |
Chinna Prudvi, Quinn W. Merrill, Derek T. Bachand, Harish Kumar, Brent E. Lince |
2002-04-23 |
| 6269465 |
Error correction system in a processing agent having minimal delay |
David L. Hill, Chinna Prudvi, Derek T. Bachand |
2001-07-31 |
| 6078981 |
Transaction stall technique to prevent livelock in multiple-processor systems |
David L. Hill, Chinna Prudvi, Derek T. Bachand, Matthew A. Fisch |
2000-06-20 |