Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9588771 | Instruction set architecture-based inter-sequencer communications with a heterogeneous resource | Hong Wang, John Shen, Hong Jiang, Richard Hankins, Per Hammarlund +8 more | 2017-03-07 |
| 9459874 | Instruction set architecture-based inter-sequencer communications with a heterogeneous resource | Hong Wang, John Shen, Hong Jiang, Richard Hankins, Per Hammarlund +8 more | 2016-10-04 |
| 8914618 | Instruction set architecture-based inter-sequencer communications with a heterogeneous resource | Hong Wang, John Shen, Hong Jiang, Richard Hankins, Per Hammarlund +8 more | 2014-12-16 |
| 7917789 | System and method for selecting optimal processor performance levels by using processor hardware feedback mechanisms | Russell J. Fenger, Anil Aggarwal | 2011-03-29 |
| 7810083 | Mechanism to emulate user-level multithreading on an OS-sequestered sequencer | Gautham Chinya, Hong Wang, Xiang Zou, James P. Held, Prashant Sethi +7 more | 2010-10-05 |
| 7363474 | Method and apparatus for suspending execution of a thread until a specified memory access occurs | Dion Rodgers, Deborah T. Marr, David L. Hill, James B. Crossland, David A. Koufaty | 2008-04-22 |
| 7127561 | Coherency techniques for suspending execution of a thread until a specified memory access occurs | David L. Hill, Deborah T. Marr, Dion Rodgers, James B. Crossland, David A. Koufaty | 2006-10-24 |