Issued Patents All Time
Showing 26–33 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5682516 | Computer system that maintains system wide cache coherency during deferred communication transactions | Nitin V. Sarangdhar, Wen-Han Wang, Michael W. Rhodehamel, James M. Brayton, Amit Merchant | 1997-10-28 |
| 5581782 | Computer system with distributed bus arbitration scheme for symmetric and priority agents | Nitin V. Sarangdhar, Konrad K. Lai, Gurbir Singh, Michael W. Rhodehamel | 1996-12-03 |
| 5572702 | Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency | Nitin V. Sarangdhar, Michael W. Rhodehamel, Amit Merchant, James M. Brayton | 1996-11-05 |
| 5572703 | Method and apparatus for snoop stretching using signals that convey snoop results | Peter D. MacWilliams, Nitin V. Sarangdhar, Amit Merchant | 1996-11-05 |
| 5551005 | Apparatus and method of handling race conditions in mesi-based multiprocessor system with private caches | Nitin V. Sarangdhar, Wen-Hann Wang | 1996-08-27 |
| 5548733 | Method and apparatus for dynamically controlling the current maximum depth of a pipe lined computer bus system | Nitin V. Sarangdhar, Michael W. Rhodehamel | 1996-08-20 |
| 5535345 | Method and apparatus for sequencing misaligned external bus transactions in which the order of completion of corresponding split transaction requests is guaranteed | James M. Brayton, Ajay Malhotra | 1996-07-09 |
| 5515516 | Initialization mechanism for symmetric arbitration agents | Michael W. Rhodehamel, Nitin V. Sarangdhar | 1996-05-07 |