Issued Patents All Time
Showing 25 most recent of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10078612 | Mode selective balanced encoded interconnect | Stephen H. Hall, Chaitanya Sreerama, Olufemi B. Oluwafemi, Antonio Zenteno Ramirez, Maynard C. Falconer | 2018-09-18 |
| 9910814 | Method, apparatus and system for single-ended communication of transaction layer packets | Bryan L. Spry, Su Wei Lim, Mikal C. Hunsaker, Rohit Verma, Lily P. Looi +2 more | 2018-03-06 |
| 9632961 | Crosstalk aware decoding for a data bus | Olufemi B. Oluwafemi, Stephen H. Hall, Jason A. Mix, Earl J. Wight, Chaitanya Sreerama +1 more | 2017-04-25 |
| 9391378 | High bandwidth connector for internal and external IO interfaces | Yun Ling, Kuan-Yu Chen, Kai Wang, Xiang Li, Howard L. Heck | 2016-07-12 |
| 9330039 | Crosstalk aware encoding for a data bus | Stephen H. Hall, Chaitanya Sreerama, Jason A. Mix, Jose A. Sanchez Sanchez, Olufemi B. Oluwafemi +2 more | 2016-05-03 |
| 8775991 | Interchangeable connection arrays for double-sided DIMM placement | Kuljit S. Bains, John T. Sprietsma | 2014-07-08 |
| 8649262 | Dynamic configuration of potential links between processing elements | Sadagopan Srinivasan, Bin Li, Michael Espig | 2014-02-11 |
| 8631208 | Providing address range coherency capability to a device | Zhen Fang, David J. Harriman | 2014-01-14 |
| 8438515 | Interchangeable connection arrays for double-sided DIMM placement | Kuljit S. Bains, John T. Sprietsma | 2013-05-07 |
| 8099687 | Interchangeable connection arrays for double-sided DIMM placement | Kuljit S. Bains, John T. Sprietsma | 2012-01-17 |
| 7772708 | Stacking integrated circuit dies | James A. McCall, Ajit Deosthali, Brad Larson | 2010-08-10 |
| 7514773 | Systems and arrangements for interconnecting integrated circuit dies | James A. McCall | 2009-04-07 |
| 7402048 | Technique for blind-mating daughtercard to mainboard | Pascal Meier, Mohiuddin M. Mazumder, Mark B. Trobough, Alok Tripathi, Ven Holalkere | 2008-07-22 |
| 7194572 | Memory system and method to reduce reflection and signal degradation | James A. McCall | 2007-03-20 |
| 7133962 | Circulator chain memory command and address bus topology | James A. McCall | 2006-11-07 |
| 6918078 | Systems with modules sharing terminations | James A. McCall | 2005-07-12 |
| 6891899 | System and method for bit encoding to increase data transfer rate | Stephen H. Hall | 2005-05-10 |
| 6788222 | Low weight data encoding for minimal power delivery impact | Stephen H. Hall | 2004-09-07 |
| 6724082 | Systems having modules with selectable on die terminations | James A. McCall, Hing Y. To | 2004-04-20 |
| 6711640 | Split delay transmission line | James A. McCall | 2004-03-23 |
| 6708243 | Computer assembly with stub traces coupled to vias to add capacitance at the vias | James A. McCall | 2004-03-16 |
| 6686762 | Memory module using DRAM package to match channel impedance | James A. McCall | 2004-02-03 |
| 6631083 | Systems with modules and clocking therefore | James A. McCall, Hing Y. To | 2003-10-07 |
| 6587912 | Method and apparatus for implementing multiple memory buses on a memory module | Bryce Horine, Randy M. Bonella, Peter D. MacWilliams | 2003-07-01 |
| 6539449 | Capacitively loaded continuity module | James A. McCall | 2003-03-25 |