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USPTO Patent Rankings Data through Dec 31, 2025
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Alok Tripathi — 16 Patents

Intel: 6 patents #6,200 of 30,777Top 25%
SNStmicroelectronics International N.V.: 5 patents #127 of 696Top 20%
CSCadence Design Systems: 3 patents #541 of 2,263Top 25%
SSStmicroelectronics Sa: 3 patents #1,912 of 4,662Top 45%
SSStmicroelectronics (Crolles 2) Sas: 1 patents #308 of 529Top 60%
UAUS Army: 1 patents #2,854 of 6,974Top 45%
Overall (All Time): #284,196 of 4,157,543Top 7%
16 Patents All Time
Alok Tripathi has been granted 16 US patents while listed as an inventor at Intel. The first was granted in 1993 and the most recent in April 2020. Alok Tripathi ranks #284,196 of 4,157,543 US inventors in our database (top 6.8%). Patent records list Alok Tripathi in Ghaziabad, MA, IN.

Issued Patents All Time

Showing 1–16 of 16 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
10637447 Low voltage, master-slave flip-flop Amit Verma, Anuj Grover, Deepak Kumar Bihani, Tanmoy Roy, Tanuj Agrawal 2020-04-28
10585143 Flip flop of a digital electronic chip Pascal Urard, Florian Cacho, Vincent Huard 2020-03-10 $24,845,000
10277207 Low voltage, master-slave flip-flop Amit Verma, Anuj Grover, Deepak Kumar Bihani, Tanmoy Roy, Tanuj Agrawal 2019-04-30 $13,912,000
10263603 Method for managing the operation of a synchronous retention flip-flop circuit exhibiting an ultra-low leakage current, and corresponding circuit Pascal Urard 2019-04-16 $9,099,000
10153754 Method for managing the operation of a low-complexity synchronous retention flip-flop circuit, and corresponding circuit Amit Verma, Pascal Urard 2018-12-11 $6,247,000
9785141 Method, system, and computer program product for schematic driven, unified thermal and electromagnetic interference compliance analyses for electronic circuit designs An-Yu Kuo, Bradley Brim, Taranjit Singh Kukal 2017-10-10 $18,422,000
9401715 Conditional pulse generator circuit for low power pulse triggered flip flop Priyankar Mathuria 2016-07-26 $7,871,000
8601422 Method and system for schematic-visualization driven topologically-equivalent layout design in RFSiP Abha Jain, Parag Choudhary, Utpal Bhattacharya 2013-12-03 $5,039,000
7490309 Method and system for automatically optimizing physical implementation of an electronic circuit responsive to simulation analysis Taranjit Singh Kukal 2009-02-10 $20,535,000
7402048 Technique for blind-mating daughtercard to mainboard Pascal Meier, Michael W. Leddige, Mohiuddin M. Mazumder, Mark B. Trobough, Ven Holalkere 2008-07-22 $18,979,000
7391829 Apparatus, system and method for receiver equalization Ken Drottar, Dave Dunning 2008-06-24 $20,489,000
7307492 Design, layout and method of manufacture for a circuit that taps a differential signal Dennis J. Miller 2007-12-11 $21,506,000
6801043 Time domain reflectometry based transmitter equalization Ken Drottar 2004-10-05 $22,015,000
6710266 Add-in card edge-finger design/stackup to optimize connector performance Jason A. Mix, Yun Ling, Kent E. Mallory 2004-03-23 $37,745,000
6700455 Electromagnetic emission reduction technique for shielded connectors Dennis J. Miller 2004-03-02 $51,169,000
5254210 Method and apparatus for growing semiconductor heterostructures Kenneth A. Jones, Joseph Flemish, Vladimir Sinisa Ban 1993-10-19