RS

Raymond L. Strouble

Fujitsu Limited: 8 patents #3,989 of 24,456Top 20%
FC Fujitsu Network Communications: 8 patents #6 of 170Top 4%
DE Digital Equipment: 3 patents #412 of 2,100Top 20%
📍 Southbridge, MA: #7 of 90 inventorsTop 8%
🗺 Massachusetts: #10,511 of 88,656 inventorsTop 15%
Overall (All Time): #427,700 of 4,157,543Top 15%
12
Patents All Time

Issued Patents All Time

Showing 1–12 of 12 patents

Patent #TitleCo-InventorsDate
6425107 Data encoder/decoder for a high speed serial link Stephen A. Caldara, Michael Sluyski 2002-07-23
6256674 Method and apparatus for providing buffer state flow control at the link level in addition to flow control on a per-connection basis Thomas A. Manning, Stephen A. Caldara, Stephen A. Hauser, Douglas H. Hunt 2001-07-03
6195764 Data encoder/decoder for a high speed serial link Stephen A. Caldara, Michael Sluyski 2001-02-27
6049901 Test system for integrated circuits using a single memory for both the parallel and scan modes of testing Mary C. Stock, Ernest P. Walker 2000-04-11
5996019 Network link access scheduling using a plurality of prioritized lists containing queue identifiers Stephen A. Hauser, Richard G. Bubenik, Stephen A. Caldara, Michael E. Gaddis, Thomas A. Manning +1 more 1999-11-30
5982771 Controlling bandwidth allocation using a pace counter Stephen A. Caldara, Stephen A. Hauser, Thomas A. Manning 1999-11-09
5896511 Method and apparatus for providing buffer state flow control at the link level in addition to flow control on a per-connection basis Thomas A. Manning, Stephen A. Caldara, Stephen A. Hauser, Douglas H. Hunt 1999-04-20
5872769 Linked list structures for multiple levels of control in an ATM switch Stephen A. Caldara, Stephen A. Hauser, Thomas A. Manning 1999-02-16
5781533 Link buffer sharing method and apparatus Thomas A. Manning, Stephen A. Hauser, Stephen A. Caldara, Douglas H. Hunt 1998-07-14
5347648 Ensuring write ordering under writeback cache error conditions Rebecca L. Stamm, Ruth I. Bahar, Nicholas D. Wade, John H. Edmondson 1994-09-13
5317720 Processor system with writeback cache using writeback and non writeback transactions stored in separate queues Rebecca L. Stamm, John H. Edmondson, David W. Archer, Samyojita Nadkarni 1994-05-31
5155843 Error transition mode for multi-processor system Rebecca L. Stamm, R. Iris Bahar, Michael A. Callander, Linda Chao, Derrick R. Meyer +3 more 1992-10-13