Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7941776 | Method of IC design optimization via creation of design-specific cells from post-layout patterns | Purnabha Majumder, Balakrishna Kumthekar, Nimish Rameshbhai Shah, John Mowchenko, Pramit Anikumar Chavda +2 more | 2011-05-10 |
| 7225423 | Method for automated design of integrated circuits with targeted quality objectives using dynamically generated building blocks | Debashis Bhattacharya, Rabindra K. Roy, Jayanta Roy | 2007-05-29 |
| 7003738 | Process for automated generation of design-specific complex functional blocks to improve quality of synthesized digital integrated circuits in CMOS using altering process | Debashis Bhattacharya, Rajeev Murgai, Rabindra K. Roy | 2006-02-21 |
| 6938223 | Logic circuit having a functionally redundant transistor network | Debashis Bhattacharya | 2005-08-30 |
| 6782514 | Context-sensitive constraint driven uniquification and characterization of standard cells | Debashis Bhattacharya | 2004-08-24 |
| 6532440 | Multiple error and fault diagnosis based on Xlists | Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita | 2003-03-11 |
| 6408424 | Verification of sequential circuits with same state encoding | Rajarshi Mukherjee, Jawahar Jain | 2002-06-18 |