Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12073156 | Propagating physical design information through logical design hierarchy of an electronic circuit | Amit Jalota, Andrew T. Saunders, Aruna Kanagaraj, Douglas Chang, Eshwari Rajendran +4 more | 2024-08-27 |
| 7890904 | Estimating jitter in a clock tree of a circuit and synthesizing a jitter-aware and skew-aware clock tree | William W. Walker | 2011-02-15 |
| 7802215 | System and method for providing an improved sliding window scheme for clock mesh analysis | Subodh M. Reddy | 2010-09-21 |
| 7801718 | Analyzing timing uncertainty in mesh-based architectures | Subodh M. Reddy, Gustavo R. Wilke | 2010-09-21 |
| 7788613 | Border-enhanced sliding window scheme (SWS) for determining clock timing in a mesh-based clock architecture | William W. Walker, Subodh M. Reddy | 2010-08-31 |
| 7725852 | Sliding window scheme (SWS) for determining clock timing in a mesh-based clock architecture | Hongyu Chen, William W. Walker | 2010-05-25 |
| 7383522 | Crosstalk-aware timing analysis | Yinghua Li, Takashi Miyoshi | 2008-06-03 |
| 7313771 | Computing current in a digital circuit based on an accurate current model for library cells | Subodh M. Reddy | 2007-12-25 |
| 7246335 | Analyzing substrate noise | Subodh M. Reddy, Takashi Miyoshi, Takeshi Horie, Mehdi Baradaran Tahoori | 2007-07-17 |
| 7197732 | Layout-driven, area-constrained design optimization | — | 2007-03-27 |
| 7003738 | Process for automated generation of design-specific complex functional blocks to improve quality of synthesized digital integrated circuits in CMOS using altering process | Debashis Bhattacharya, Vamsi Boppana, Rabindra K. Roy | 2006-02-21 |