Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11668750 | Performing testing utilizing staggered clocks | Sailendra Chadalavada, Venkat Abilash Reddy Nerallapally, Jaison Daniel Kurien, Bonita Bhaskaran, Milind Sonawane +1 more | 2023-06-06 |
| 7941776 | Method of IC design optimization via creation of design-specific cells from post-layout patterns | Balakrishna Kumthekar, Nimish Rameshbhai Shah, John Mowchenko, Pramit Anikumar Chavda, Yoshihisa Kojima +2 more | 2011-05-10 |