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Low-power static signoff verification from within an implementation tool |
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2024-04-02 |
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Implementing and verifying safety measures in a system design based on safety specification generated from safety requirements |
Meirav O. Nitzan, Stewart Williams |
2023-01-10 |
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Machine learning (ML)-based static verification for derived hardware-design elements |
Rajarshi Mukherjee, Paras Mal Jain, David L. Allen |
2022-10-11 |
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State table complexity reduction in a hierarchical verification flow |
Rajarshi Mukherjee, David L. Allen, Bhaskar Pal, Sanjay Gulati, Gaurav PRATAP +3 more |
2022-01-11 |
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Apparatuses and methods for accurate and efficient clock domain and reset domain verification with register transfer level memory inference |
Dipti Ranjan Senapati, Fahim Rahim |
2020-12-29 |
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Voltage reconciliation in multi-level power managed systems |
David L. Allen |
2020-07-07 |
| 9886753 |
Verification of circuit structures including sub-structure variants |
Mahantesh D. Narwade, Namit Gupta, Rajarshi Mukherjee, Suman Nandan, Subhamoy Pal |
2018-02-06 |
| 9792394 |
Accurate glitch detection |
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2017-10-17 |
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Minimizing crossover paths for functional verification of a circuit description |
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2016-12-27 |
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Ranking verification results for root cause analysis |
Kevin M. Harer, Rajarshi Mukherjee, Mahantesh D. Narwade |
2015-05-12 |
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Technique for honoring multi-cycle path semantics in RTL simulation |
Badri P. Gopalan, Dhiraj Goswami |
2013-07-02 |
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Method and apparatus for extracting assume properties from a constrained random test-bench |
Eduard Cerny, Pallab Dasgupta, Bhaskar Pal, Partha Pratim Chakrabarti |
2010-09-14 |
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IDDQ test solution for large asics |
Venkat C. Ghanta, Arun Gunda |
2001-04-03 |
| 6135647 |
System and method for representing a system level RTL design using HDL independent objects and translation to synthesizable RTL code |
Arun Balakrishnan, Jun Qian |
2000-10-24 |
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Test shells for protecting proprietary information in asic cores |
Siva Venkatraman, Arun Gunda |
1999-05-11 |
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Defect isolation using scan-path testing and electron beam probing in multi-level high density asics |
Grant Lindberg, Sharad Prasad, Arun Gunda |
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Protecting proprietary asic design information using boundary scan on selective inputs and outputs |
— |
1997-06-10 |