KD

Kaushik De

SY Synopsys: 12 patents #67 of 2,302Top 3%
Lsi Logic: 5 patents #372 of 1,957Top 20%
Overall (All Time): #267,740 of 4,157,543Top 7%
17
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11947885 Low-power static signoff verification from within an implementation tool Meera Viswanath, David L. Allen, Sabyasachi Das, Renu Mehra, Godwin R. Maben 2024-04-02
11550979 Implementing and verifying safety measures in a system design based on safety specification generated from safety requirements Meirav O. Nitzan, Stewart Williams 2023-01-10
11467851 Machine learning (ML)-based static verification for derived hardware-design elements Rajarshi Mukherjee, Paras Mal Jain, David L. Allen 2022-10-11
11222154 State table complexity reduction in a hierarchical verification flow Rajarshi Mukherjee, David L. Allen, Bhaskar Pal, Sanjay Gulati, Gaurav PRATAP +3 more 2022-01-11
10878153 Apparatuses and methods for accurate and efficient clock domain and reset domain verification with register transfer level memory inference Dipti Ranjan Senapati, Fahim Rahim 2020-12-29
10706192 Voltage reconciliation in multi-level power managed systems David L. Allen 2020-07-07
9886753 Verification of circuit structures including sub-structure variants Mahantesh D. Narwade, Namit Gupta, Rajarshi Mukherjee, Suman Nandan, Subhamoy Pal 2018-02-06
9792394 Accurate glitch detection Dipti Ranjan Senapati, Mahantesh D. Narwade, Namit Gupta, Rajarshi Mukherjee 2017-10-17
9529948 Minimizing crossover paths for functional verification of a circuit description Mahantesh D. Narwade, Rajarshi Mukherjee, Namit Gupta 2016-12-27
9032339 Ranking verification results for root cause analysis Kevin M. Harer, Rajarshi Mukherjee, Mahantesh D. Narwade 2015-05-12
8479128 Technique for honoring multi-cycle path semantics in RTL simulation Badri P. Gopalan, Dhiraj Goswami 2013-07-02
7797123 Method and apparatus for extracting assume properties from a constrained random test-bench Eduard Cerny, Pallab Dasgupta, Bhaskar Pal, Partha Pratim Chakrabarti 2010-09-14
6212655 IDDQ test solution for large asics Venkat C. Ghanta, Arun Gunda 2001-04-03
6135647 System and method for representing a system level RTL design using HDL independent objects and translation to synthesizable RTL code Arun Balakrishnan, Jun Qian 2000-10-24
5903578 Test shells for protecting proprietary information in asic cores Siva Venkatraman, Arun Gunda 1999-05-11
5663967 Defect isolation using scan-path testing and electron beam probing in multi-level high density asics Grant Lindberg, Sharad Prasad, Arun Gunda 1997-09-02
5638380 Protecting proprietary asic design information using boundary scan on selective inputs and outputs 1997-06-10