Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11544435 | On-the-fly computation of analog mixed-signal (AMS) measurements | Dmitry Korchemny, Ilya Kudryavtsev, Dmitriy Mosheyev | 2023-01-03 |
| 11501050 | Analog mixed-signal assertion-based checker system | Dmitry Korchemny, Ilya Kudryavtsev | 2022-11-15 |
| 11188695 | Unified functional coverage and synthesis flow for formal verification and emulation | Dmitry Korchemny, Ashok Kumar Bhatt, Hanish Singla | 2021-11-30 |
| 10846455 | Automatic definition and extraction of functional coverage metric for emulation-based verification | Saptarshi Ghosh, Yogesh Pandey, Sivaprasad Acharya | 2020-11-24 |
| 10831956 | Efficient execution of alternating automaton representing a safety assertion for a circuit | Gerald Taylor | 2020-11-10 |
| 9626468 | Assertion extraction from design and its signal traces | Diganchal Chakraborty, Saptarshi Ghosh, Yogesh Pandey | 2017-04-18 |
| 8527921 | Constrained random simulation coverage closure guided by a cover property | Surrendra A. Dudani, William R. Dufresne | 2013-09-03 |
| 8448109 | Vector evaluation of assertions | Surrendra A. Dudani, Samik Sengupta | 2013-05-21 |
| 7797123 | Method and apparatus for extracting assume properties from a constrained random test-bench | Kaushik De, Pallab Dasgupta, Bhaskar Pal, Partha Pratim Chakrabarti | 2010-09-14 |
| 7454727 | Method and Apparatus for Solving Sequential Constraints | Ashvin M. Dsouza, Kevin M. Harer, Pei-Hsin Ho | 2008-11-18 |
| 7076753 | Method and apparatus for solving sequential constraints | Ashvin M. Dsouza, Kevin M. Harer, Pei-Hsin Ho | 2006-07-11 |
| 6363520 | Method for testability analysis and test point insertion at the RT-level of a hardware development language (HDL) specification | Samir Boubezari, Bozena Kaminska, Benoit Nadeau-Dostie | 2002-03-26 |