Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12254255 | Glitch identification and power analysis using simulation vectors | Joydeep Banerjee, Mayur Bubna, Debabrata Das Roy | 2025-03-18 |
| 12124780 | Power estimation using input vectors and deep recurrent neural networks | Chaofan Wang, Vaibhav Jain, Shekaripuram V. Venkatesh | 2024-10-22 |
| 12093620 | Multi-cycle power analysis of integrated circuit designs | George Chen | 2024-09-17 |
| 12001317 | Waveform based reconstruction for emulation | Gagan Vishal Jain, Johnson Adaikalasamy, Alexander John Wakefield, Ritesh Mittal, Olivier Coudert | 2024-06-04 |
| 12001768 | Enhanced glitch estimation in vectorless power analysis | Qing Su, Pankaj Singla, Eduard Petrus Huijbregts, Stephan Houben | 2024-06-04 |
| 11842132 | Multi-cycle power analysis of integrated circuit designs | George Chen | 2023-12-12 |
| 11726899 | Waveform based reconstruction for emulation | Gagan Vishal Jain, Johnson Adaikalasamy, Alexander John Wakefield, Ritesh Mittal, Olivier Coudert | 2023-08-15 |
| 11651131 | Glitch source identification and ranking | Vaibhav Jain, Myunghoon Yoon, Qing Su | 2023-05-16 |
| 11651129 | Selecting a subset of training data from a data pool for a power prediction model | Chaofan Wang, Vaibhav Jain, Shekaripuram V. Venkatesh | 2023-05-16 |
| 11200149 | Waveform based reconstruction for emulation | Gagan Vishal Jain, Johnson Adaikalasamy, Alexander John Wakefield, Ritesh Mittal, Olivier Coudert | 2021-12-14 |
| 10621296 | Generating SAIF efficiently from hardware platforms | Boris Gommershtadt, Alexander John Wakefield, Lakshmi Narayana Koduri Hanumath Prasad | 2020-04-14 |
| 9405872 | System and method for reducing power of a circuit using critical signal analysis | Sean Safarpour, Shekaripuram V. Venkatesh, Siddharth Guha, Fahim Rahim | 2016-08-02 |
| 8984469 | System and method for strengthening of a circuit element to reduce an integrated circuit's power consumption | Mohammad H. Movahed-Ezazi, Siddharth Guha, Vaibhav Jain | 2015-03-17 |
| 8677295 | Sequential clock gating using net activity and xor technique on semiconductor designs including already gated pipeline design | Mohammad H. Movahed-Ezazi | 2014-03-18 |
| 8656326 | Sequential clock gating using net activity and XOR technique on semiconductor designs including already gated pipeline design | Mohammad H. Movahed-Ezazi | 2014-02-18 |
| 8635578 | System and method for strengthening of a circuit element to reduce an integrated circuit's power consumption | Mohammad H. Movahed-Ezazi, Siddharth Guha, Vaibhav Jain | 2014-01-21 |
| 8285527 | Method and system for equivalence checking | Pradeep Kumar Nalla | 2012-10-09 |
| 8042085 | Method for compaction of timing exception paths | Manish Bhatia, Housseine Rejouan | 2011-10-18 |
| 7650581 | Method for modeling and verifying timing exceptions | Mayank Jain | 2010-01-19 |