Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12001768 | Enhanced glitch estimation in vectorless power analysis | Pankaj Singla, Solaiman Rahim, Eduard Petrus Huijbregts, Stephan Houben | 2024-06-04 |
| 11651131 | Glitch source identification and ranking | Vaibhav Jain, Solaiman Rahim, Myunghoon Yoon | 2023-05-16 |
| 11531797 | Vector generation for maximum instantaneous peak power | Youxin Gao, Mayur Bubna | 2022-12-20 |
| 8999766 | ESD/antenna diodes for through-silicon vias | Min Ni, Zongwu Tang, Jamil Kawa, James David Sproch | 2015-04-07 |
| 8877638 | ESD/antenna diodes for through-silicon vias | Jamil Kawa, Min Ni, James David Sproch, Zongwu Tang | 2014-11-04 |
| 8762918 | Banded computation architectures | Min Ni, Zongwu Tang | 2014-06-24 |
| 8458635 | Convolution computation for many-core processor architectures | Min Ni, Zongwu Tang | 2013-06-04 |
| 8264065 | ESD/antenna diodes for through-silicon vias | Min Ni, Zongwu Tang, Jamil Kawa, James David Sproch | 2012-09-11 |
| 8205185 | Fast evaluation of average critical area for IC layouts | Subarnarekha Sinha, Charles C. Chiang | 2012-06-19 |
| 8205179 | Fast evaluation of average critical area for IC layouts | Subarnarekha Sinha, Charles C. Chiang | 2012-06-19 |
| 8151236 | Steiner tree based approach for polygon fracturing | Yongqiang Lu, Charles C. Chiang | 2012-04-03 |
| 8000826 | Predicting IC manufacturing yield by considering both systematic and random intra-die process variations | Jianfeng Luo, Subarnarekha Sinha, Charles C. Chiang | 2011-08-16 |
| 7962873 | Fast evaluation of average critical area for ic layouts | Subarnarekha Sinha, Charles C. Chiang | 2011-06-14 |
| 7962882 | Fast evaluation of average critical area for IC layouts | Subarnarekha Sinha, Charles C. Chiang | 2011-06-14 |
| 7707526 | Predicting IC manufacturing yield based on hotspots | Charles C. Chiang | 2010-04-27 |
| 7679872 | Electrostatic-discharge protection using a micro-electromechanical-system switch | Jamil Kawa, Subarnarekha Sinha, Min-Chun Tsai, Zongwu Tang | 2010-03-16 |
| 7543255 | Method and apparatus to reduce random yield loss | Subarnarekha Sinha, Charles C. Chiang | 2009-06-02 |
| 7346865 | Fast evaluation of average critical area for IC layouts | Subarnarekha Sinha, Charles C. Chiang | 2008-03-18 |
| 7289933 | Simulating topography of a conductive material in a semiconductor wafer | Jianfeng Luo, Charles C. Chiang | 2007-10-30 |