Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Charles C. Chiang — 31 Patents

SYSynopsys: 31 patents #10 of 2,302Top 1%
Saratoga, CA: #321 of 2,933 inventorsTop 15%
California: #16,606 of 386,348 inventorsTop 5%
Overall (All Time): #115,823 of 4,157,543Top 3%
31 Patents All Time
Charles C. Chiang has been granted 31 US patents while listed as an inventor at Synopsys. The first was granted in 2007 and the most recent in August 2022. Charles C. Chiang ranks #115,823 of 4,157,543 US inventors in our database (top 2.8%). Patent records list Charles C. Chiang in Saratoga, CA, US.

Issued Patents All Time

Showing 1–25 of 31 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
11403564 Lithographic hotspot detection using multiple machine learning kernels Yen-Ting Yu, Geng-He Lin, Hui-Ru Jiang 2022-08-02 $73,386,000
9594867 DRC-based hotspot detection considering edge tolerance and incomplete specification Yen-Ting Yu, Hui-Ru Jiang, Yumin Zhang 2017-03-14 $16,500,000
9098649 Distance metric for accurate lithographic hotspot classification using radial and angular functions Jing Guo, Fan Yang, Subarnarekha Sinha, Xuan Zeng 2015-08-04 $12,754,000
8635580 Preconditioning for EDA cell library Xin Wang 2014-01-21 $6,821,000
8601419 Accurate process hotspot detection using critical design rule extraction Yen-Ting Yu, Hui-Ru Jiang, Subarnarekha Sinha, Ya-Chung Chan 2013-12-03 $4,231,000
8490030 Distance metric for accurate lithographic hotspot classification using radial and angular functions Jing Guo, Fan Yang, Subarnarekha Sinha, Xuan Zeng 2013-07-16 $6,727,000
8452075 Range pattern matching for hotspots containing vias and incompletely specified range patterns Jingyu Xu, Subarnarekha Sinha 2013-05-28 $4,195,000
8286121 Preconditioning for EDA cell library Xin Wang 2012-10-09 $4,365,000
8219941 Range pattern definition of susceptibility of layout regions to fabrication issues Subarnarekha Sinha 2012-07-10 $3,650,000
8209639 Identifying layout regions susceptible to fabrication issues by using range patterns Subarnarekha Sinha, Hailong Yao 2012-06-26 $5,356,000
8205179 Fast evaluation of average critical area for IC layouts Qing Su, Subarnarekha Sinha 2012-06-19 $3,229,000
8205185 Fast evaluation of average critical area for IC layouts Qing Su, Subarnarekha Sinha 2012-06-19 $3,229,000
8176456 Method and apparatus for computing dummy feature density for chemical-mechanical polishing Xin Wang, Jamil Kawa 2012-05-08 $7,909,000
8151236 Steiner tree based approach for polygon fracturing Qing Su, Yongqiang Lu 2012-04-03 $5,527,000
8146032 Method and apparatus for performing RLC modeling and extraction for three-dimensional integrated circuit (3D-IC) designs Qiushi CHEN, Beifang Qiu, Xiaoping Hu, Mathew Koshy, Baribrata Biswas 2012-03-27 $6,043,000
8141007 Method and apparatus for identifying and correcting phase conflicts Subarnarekha Sinha 2012-03-20 $5,494,000
8006212 Method and system for facilitating floorplanning for 3D IC Subarnarekha Sinha 2011-08-23 $2,981,000
8000826 Predicting IC manufacturing yield by considering both systematic and random intra-die process variations Jianfeng Luo, Subarnarekha Sinha, Qing Su 2011-08-16 $2,617,000
7962873 Fast evaluation of average critical area for ic layouts Qing Su, Subarnarekha Sinha 2011-06-14 $2,204,000
7962882 Fast evaluation of average critical area for IC layouts Qing Su, Subarnarekha Sinha 2011-06-14 $2,204,000
7823099 Lithography suspect spot location and scoring system Min-Chun Tsai 2010-10-26 $7,257,000
7707526 Predicting IC manufacturing yield based on hotspots Qing Su 2010-04-27 $5,390,000
7703067 Range pattern definition of susceptibility of layout regions to fabrication issues Subarnarekha Sinha 2010-04-20 $7,829,000
7644378 Preconditioning for EDA cell library Xin Wang 2010-01-05 $17,111,000
7594213 Method and apparatus for computing dummy feature density for chemical-mechanical polishing Xin Wang, Jamil Kawa 2009-09-22 $13,303,000