Issued Patents All Time
Showing 26–31 of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7543255 | Method and apparatus to reduce random yield loss | Subarnarekha Sinha, Qing Su | 2009-06-02 |
| 7509622 | Dummy filling technique for improved planarization of chip surface topography | Subarnarekha Sinha, Jianfeng Luo | 2009-03-24 |
| 7503029 | Identifying layout regions susceptible to fabrication issues by using range patterns | Subarnarekha Sinha, Hailong Yao | 2009-03-10 |
| 7496883 | Method and apparatus for identifying and correcting phase conflicts | Subarnarekha Sinha | 2009-02-24 |
| 7346865 | Fast evaluation of average critical area for IC layouts | Qing Su, Subarnarekha Sinha | 2008-03-18 |
| 7289933 | Simulating topography of a conductive material in a semiconductor wafer | Jianfeng Luo, Qing Su | 2007-10-30 |