Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10970454 | Scalable connectivity verification using conditional cut-points | Raj Kumar Gajavelly, Jason R. Baumgartner, Raja Bilwakeshwar Ivaturi | 2021-04-06 |
| 10621297 | Initial-state and next-state value folding | Jason R. Baumgartner, Robert L. Kanzelman, Raj Kumar Gajavelly, Dheeraj Baby | 2020-04-14 |
| 10579770 | Scalable connectivity verification using conditional cut-points | Raj Kumar Gajavelly, Jason R. Baumgartner, Raja Bilwakeshwar Ivaturi | 2020-03-03 |
| 10540468 | Verification complexity reduction via range-preserving input-to-constant conversion | Raj Kumar Gajavelly, Jason R. Baumgartner, Robert L. Kanzelman, Alexander Ivrii | 2020-01-21 |
| 10474777 | Scalable liveness verification | Jason R. Baumgartner, Raj Kumar Gajavelly, Alexander Ivrii | 2019-11-12 |
| 10394987 | Adaptive bug-search depth for simple and deep counterexamples | Jason R. Baumgartner, Raj Kumar Gajavelly, Hari Mony | 2019-08-27 |
| 10354028 | Formal verification driven power modeling and design verification | Anand Haridass, Arun Joseph, Rahul M. Rao | 2019-07-16 |
| 10210296 | Adaptive bug-search depth for simple and deep counterexamples | Jason R. Baumgartner, Raj Kumar Gajavelly, Hari Mony | 2019-02-19 |
| 10078716 | Scalable logic verification by identifying unate primary inputs | Jason R. Baumgartner, Raj Kumar Gajavelly, Alexander Ivrii | 2018-09-18 |
| 10073938 | Integrated circuit design verification | Anand B. Arunagiri, Raj Kumar Gajavelly, Sujeet Kumar | 2018-09-11 |
| 9934873 | Delayed equivalence identification | Raj Kumar Gajavelly, Ashutosh Misra, Rahul M. Rao | 2018-04-03 |
| 9922153 | Scalable logic verification by identifying unate primary inputs | Jason R. Baumgartner, Raj Kumar Gajavelly, Alexander Ivrii | 2018-03-20 |
| 9740589 | Lifting of bounded liveness counterexamples to concrete liveness counterexamples | Jason R. Baumgartner, Raj Kumar Gajavelly, Alexander Ivrii | 2017-08-22 |
| 9715564 | Scalable and automated identification of unobservability causality in logic optimization flows | Jason R. Baumgartner, Raj Kumar Gajavelly, Ashutosh Misra | 2017-07-25 |
| 9697306 | Formal verification driven power modeling and design verification | Anand Haridass, Arun Joseph, Rahul M. Rao | 2017-07-04 |
| 9678853 | Lifting of bounded liveness counterexamples to concrete liveness counterexamples | Jason R. Baumgartner, Raj Kumar Gajavelly, Alexander Ivrii | 2017-06-13 |
| 9483595 | Method for scalable liveness verification via abstraction refinement | Jason R. Baumgartner, Raj Kumar Gajavelly, Robert L. Kanzelman, Hari Mony | 2016-11-01 |
| 9471734 | System and program product for scalable liveness verification via abstraction refinement | Jason R. Baumgartner, Raj Kumar Gajavelly, Robert L. Kanzelman, Hari Mony | 2016-10-18 |
| 9460251 | Formal verification driven power modeling and design verification | Anand Haridass, Arun Joseph, Rahul M. Rao | 2016-10-04 |
| 8285527 | Method and system for equivalence checking | Solaiman Rahim | 2012-10-09 |