Issued Patents All Time
Showing 25 most recent of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12277372 | Multi-cycle test generation and source-based simulation | Peter Wohl | 2025-04-15 |
| 12117488 | Multiple clock and clock cycle selection for x-tolerant logic built in self test (XLBIST) | Peter Wohl | 2024-10-15 |
| 11422186 | Per-shift X-tolerant logic built-in self-test | Peter Wohl | 2022-08-23 |
| 10908213 | Reducing X-masking effect for linear time compactors | Emil Gizdarski, Peter Wohl | 2021-02-02 |
| 10346557 | Increasing compression by reducing padding patterns | Peter Wohl | 2019-07-09 |
| 9404972 | Diagnosis and debug with truncated simulation | Peter Wohl, Emil Gizdarski, Wolfgang Meyer, Andrea Costa | 2016-08-02 |
| 9171123 | Diagnosis and debug using truncated simulation | Peter Wohl, Emil Gizdarski, Wolfgang Meyer, Andrea Costa | 2015-10-27 |
| 9157961 | Two-level compression through selective reseeding | Peter Wohl, Frederic J. Neuveux, Gregory A. Maston | 2015-10-13 |
| 9152752 | Increasing PRPG-based compression by delayed justification | Peter Wohl | 2015-10-06 |
| 8645780 | Fully X-tolerant, very high scan compression scan test systems and techniques | Peter Wohl, Frederic J. Neuveux | 2014-02-04 |
| 8549372 | ATPG and compression by using majority gates | Peter Wohl | 2013-10-01 |
| 8464115 | Fully X-tolerant, very high scan compression scan test systems and techniques | Peter Wohl, Frederic J. Neuveux | 2013-06-11 |
| 8429473 | Increasing PRPG-based compression by delayed justification | Peter Wohl | 2013-04-23 |
| 7979763 | Fully X-tolerant, very high scan compression scan test systems and techniques | Peter Wohl, Frederic J. Neuveux | 2011-07-12 |
| 7958472 | Increasing scan compression by using X-chains | Peter Wohl, Frederic J. Neuveux, Yasunari Kanzawa | 2011-06-07 |
| 7882410 | Launch-on-shift support for on-chip-clocking | Timothy Ayres, Peter Wohl | 2011-02-01 |
| 7823034 | Pipeline of additional storage elements to shift input/output data of combinational scan compression circuit | Peter Wohl, Frederic J. Neuveux | 2010-10-26 |
| 7814444 | Scan compression circuit and method of design therefor | Peter Wohl, Sanjay Ramnath, Rohit Kapur, Thomas W. Williams | 2010-10-12 |
| 7237162 | Deterministic BIST architecture tolerant of uncertain scan chain outputs | Peter Wohl | 2007-06-26 |
| 6993694 | Deterministic bist architecture including MISR filter | Rohit Kapur, Thomas W. Williams, Tony Taylor, Peter Wohl | 2006-01-31 |
| 6959272 | Method and system for generating an ATPG model of a memory from behavioral descriptions | Peter Wohl, Timothy G. Hunkler | 2005-10-25 |
| 6950974 | Efficient compression and application of deterministic patterns in a logic BIST architecture | Peter Wohl, Thomas W. Williams | 2005-09-27 |
| 6807646 | System and method for time slicing deterministic patterns for reseeding in logic built-in self-test | Thomas W. Williams, Peter Wohl, Rohit Kapur | 2004-10-19 |
| 6453437 | Method and system for performing transition fault simulation along long circuit paths for high-quality automatic test pattern generation | Rohit Kapur, Thomas W. Williams, Peter Wohl | 2002-09-17 |
| 6385750 | Method and system for controlling test data volume in deterministic test pattern generation | Rohit Kapur, Thomas W. Williams, Peter Wohl | 2002-05-07 |