Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11444201 | Leakage current reduction in polysilicon-on-active-edge structures | Kwanyong LIM, Youseok Suh, Hyunwoo Park | 2022-09-13 |
| 11075206 | SRAM source-drain structure | Kwanyong LIM, Ukjin Roh | 2021-07-27 |
| 10996261 | Sensor for gate leakage detection | Hyunwoo Park, Stanley Seungchul Song | 2021-05-04 |
| 10950488 | Integration of finFET device | Ryoung-Han Kim, Kwanyong LIM | 2021-03-16 |
| 10600774 | Systems and methods for fabrication of gated diodes with selective epitaxial growth | Youseok Suh, Kwanyong LIM | 2020-03-24 |
| 10490558 | Reducing or avoiding mechanical stress in static random access memory (SRAM) strap cells | Samit Sengupta, Shashank S. Ekbote | 2019-11-26 |
| 10062768 | Field-effect transistor (FET) devices employing adjacent asymmetric active gate / dummy gate width layout | Ukjin Roh, Shashank S. Ekbote | 2018-08-28 |
| 9953967 | Integrated circuit with dual stress liner boundary | Greg Baldwin | 2018-04-24 |
| 9922971 | Integration of analog transistor | Himadri Sekhar Pal, Shashank S. Ekbote | 2018-03-20 |
| 9882051 | Fin field effect transistors (FETs) (FinFETs) employing dielectric material layers to apply stress to channel regions | Ukjin Roh, Shashank S. Ekbote | 2018-01-30 |
| 9634138 | Field-effect transistor (FET) devices employing adjacent asymmetric active gate / dummy gate width layout | Ukjin Roh, Shashank S. Ekbote | 2017-04-25 |
| 9543437 | Integrated circuit with dual stress liner boundary | Greg Baldwin | 2017-01-10 |
| 9412741 | Integration of analog transistor | Himadri Sekhar Pal, Shashank S. Ekbote | 2016-08-09 |
| 9406769 | Silicide formation due to improved SiGe faceting | Shashank S. Ekbote, Kwan-Yong Lim, Ebenezer E. Eshun | 2016-08-02 |
| 9202810 | Integration of analog transistor | Himadri Sekhar Pal, Shashank S. Ekbote | 2015-12-01 |
| 9202883 | Silicide formation due to improved SiGe faceting | Shashank S. Ekbote, Kwan-Yong Lim, Ebenezer E. Eshun | 2015-12-01 |
| 9171901 | Method for improving device performance using dual stress liner boundary | Greg Baldwin | 2015-10-27 |
| 9093298 | Silicide formation due to improved SiGe faceting | Shashank S. Ekbote, Kwan-Yong Lim, Ebenezer E. Eshun | 2015-07-28 |
| 9029263 | Method of printing multiple structure widths using spacer double patterning | Ryoung-Han Kim | 2015-05-12 |
| 8987748 | Drain induced barrier lowering with anti-punch-through implant | Himadri Sekhar Pal, Amitabh Jain | 2015-03-24 |
| 8859357 | Method for improving device performance using dual stress liner boundary | Greg Baldwin | 2014-10-14 |
| 8748256 | Integrated circuit having silicide block resistor | Song Zhao, Gregory Charles Baldwin, Shashank S. Ekbote | 2014-06-10 |
| 8669775 | Scribe line test modules for in-line monitoring of context dependent effects for ICs including MOS devices | Oluwamuyiwa Oluwagbemiga Olubuyide, Gregory Charles Baldwin | 2014-03-11 |
| 8664968 | On-die parametric test modules for in-line monitoring of context dependent effects | Gregory Charles Baldwin, Thomas J. Aton, Kayvan Sadra, Oluwamuyiwa Oluwagbemiga Olubuyide | 2014-03-04 |