Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12136649 | Deep trench isolation structures with a substrate connection | Jianbo Zhou, Namchil Mun, Hung-Chang Liao, Zhongxiu Yang | 2024-11-05 |
| 11908930 | Laterally-diffused metal-oxide-semiconductor devices with a multiple-thickness buffer dielectric layer | Namchil Mun | 2024-02-20 |
| 10529819 | High voltage Schottky diode and manufacturing method thereof | Namchil Mun, Jeoung Mo Koo, Raj Verma Purakh | 2020-01-07 |
| 10510831 | Low on resistance high voltage metal oxide semiconductor transistor | Namchil Mun, Jeoung Mo Koo, Raj Verma Purakh | 2019-12-17 |
| 10504768 | Contact structures to deep trench isolation structures and method of nanufacturing the same | Ke Dong, Purakh Raj Verma, Namchil Mun | 2019-12-10 |
| 9831304 | Integrated circuits with deep trench isolations and methods for producing the same | Mun Tat Yap, Namchil Mun, Tat Wei Chua, Raj Verma Purakh, Jeoung Mo Koo | 2017-11-28 |
| 9673084 | Isolation scheme for high voltage device | Kun Liu, Francis Benistant, Ming-Shuan Li, Namchil Mun, Purakh Raj Verma | 2017-06-06 |
| 8999803 | Methods for fabricating integrated circuits with the implantation of fluorine | Nicolas Sassiat, Ran Yan, Torben Balzer | 2015-04-07 |
| 8975704 | Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations | Jan Hoentschel, Stefan Flachowsky, Thilo Scheiper | 2015-03-10 |
| 8975708 | Semiconductor device with reduced contact resistance and method of manufacturing thereof | Eng Huat Toh, Jae Gon Lee, Chung Foong Tan, Elgin Quek | 2015-03-10 |
| 8936977 | Late in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations | Jan Hoentschel, Stefan Flachowsky, Thilo Scheiper | 2015-01-20 |
| 8916430 | Methods for fabricating integrated circuits with the implantation of nitrogen | Ran Yan, Jan Hoentschel | 2014-12-23 |
| 8828834 | Methods of tailoring work function of semiconductor devices with high-k/metal layer gate structures by performing a fluorine implant process | Shesh Mani Pandey, Jan Hoentschel | 2014-09-09 |
| 8703578 | Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations | Jan Hoentschel, Stefan Flachowsky, Thilo Scheiper | 2014-04-22 |
| 8470700 | Semiconductor device with reduced contact resistance and method of manufacturing thereof | Eng Huat Toh, Jae Gon Lee, Chung Foong Tan, Elgin Quek | 2013-06-25 |
| 8440530 | Methods of forming highly scaled semiconductor devices using a disposable spacer technique | Jan Hoentschel, Stefan Flachowsky | 2013-05-14 |
| 8143651 | Nested and isolated transistors with reduced impedance difference | Johnny Widodo, Liang-Choo Hsia, James Yong Meng Lee, Wen Zhi Gao, Zhao Lun +5 more | 2012-03-27 |
| 8008744 | Selective STI stress relaxation through ion implantation | Lee-Wee Teo, Jae Gon Lee, Vincent Leong, Elgin Quek, Dong Kyun Sohn | 2011-08-30 |
| 7767577 | Nested and isolated transistors with reduced impedance difference | Johnny Widodo, Liang-Choo Hsia, James Yong Meng Lee, Wen Zhi Gao, Zhao Lun +5 more | 2010-08-03 |
| 7727856 | Selective STI stress relaxation through ion implantation | Lee-Wee Teo, Jae Gon Lee, Vincent Leong, Elgin Quek, Dong Kyun Sohn | 2010-06-01 |
| 7400018 | End of range (EOR) secondary defect engineering using chemical vapor deposition (CVD) substitutional carbon doping | Chung Foong Tan, Jinping Liu, Hyeok LEE, Bangun Indajang, Eng Fong Chor | 2008-07-15 |
| 7109099 | End of range (EOR) secondary defect engineering using substitutional carbon doping | Chung Foong Tan, Jinping Liu, Hyeok LEE, Bangun Indajang, Eng Fong Chor | 2006-09-19 |