Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7067869 | Adjustable 3D capacitor | Wei Cheng, Chit Hwei Ng, Marvin Liao | 2006-06-27 |
| 6841441 | Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing | Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Jia Zhen Zheng, Elgin Quek +1 more | 2005-01-11 |
| 6828082 | Method to pattern small features by using a re-flowable hard mask | Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Jia Zhen Zheng, Elgin Quek +1 more | 2004-12-07 |
| 6803305 | Method for forming a via in a damascene process | Wei Cheng, Yakub Aliyu, Ding Yi | 2004-10-12 |
| 6713335 | Method of self-aligning a damascene gate structure to isolation regions | Ching Thiam Chung, Wei Cheng, Chester Nieh, Tong Boon Lee | 2004-03-30 |
| 6689643 | Adjustable 3D capacitor | Wei Cheng, Chit Hwei Ng, Marvin Liao | 2004-02-10 |
| 6686279 | Method for reducing gouging during via formation | Wei Cheng, Yakub Aliyu, Lee Yuan Ping | 2004-02-03 |
| 6664153 | Method to fabricate a single gate with dual work-functions | Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Jia Zhen Zheng, Elgin Quek +1 more | 2003-12-16 |
| 6632712 | Method of fabricating variable length vertical transistors | Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Jia Zhen Zheng, Elgin Quek +1 more | 2003-10-14 |
| 6630380 | Method for making three-dimensional metal-insulator-metal capacitors for dynamic random access memory (DRAM) and ferroelectric random access memory (FERAM) | Wei Cheng, Kunihiko Takahashi, Ming Lei, Thomas Joy | 2003-10-07 |
| 6610604 | Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask | Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Jia Zhen Zheng, Elgin Quek +1 more | 2003-08-26 |
| 6610575 | Forming dual gate oxide thickness on vertical transistors by ion implantation | Chew Hoe Ang, Eng Hua Lim, Cher Liang Cha, Jia Zhen Zheng, Elgin Quek +1 more | 2003-08-26 |
| 6576526 | Darc layer for MIM process integration | Shao Kai, Wu-Guan Ping, Chen-Wei Liang, Cheng Hua, Sanford Chu | 2003-06-10 |
| 6544848 | Method to form an asymmetrical non-volatile memory device using small in-situ doped polysilicon spacers | Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Jia Zhen Zheng, Elgin Quek +1 more | 2003-04-08 |
| 6468851 | Method of fabricating CMOS device with dual gate electrode | Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Jia Zhen Zheng, Elgin Quek +1 more | 2002-10-22 |
| 6429109 | Method to form high k dielectric and silicide to reduce poly depletion by using a sacrificial metal between oxide and gate | Jia Zhen Zheng, Elgin Quek, Mei Sheng Zhou, Chew Hoe Ang, Eng Hua Lim +1 more | 2002-08-06 |
| 6004622 | Spin-on-glass process with controlled environment | Been-Yih Jin, Ming Hong Wang | 1999-12-21 |
| 5883001 | Integrated circuit passivation process and structure | Been-Yih Jin, Wen-Yen Hwang, Ming Hong Wang, Sheng Hsien Wong, Gino Hwang +4 more | 1999-03-16 |
| 5716673 | Spin-on-glass process with controlled environment | Been-Yih Jin, Ming Hong Wang | 1998-02-10 |
| 5174043 | Machine and method for high vacuum controlled ramping curing furnace for sog planarization | — | 1992-12-29 |
| 5106787 | Method for high vacuum controlled ramping curing furnace for SOG planarization | — | 1992-04-21 |
| 5003062 | Semiconductor planarization process for submicron devices | — | 1991-03-26 |