Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11668758 | High impedance cell detection | Gregory Rise, Nangavalli Ramasubramanian, Bernadette Parong | 2023-06-06 |
| 10863160 | Conditional forced perspective in spherical video | Franz Hildgen | 2020-12-08 |
| 10460501 | System and method for processing digital video | Scott Herman, Franz Hildgen | 2019-10-29 |
| 10297086 | System and method for processing digital video | Franz Hildgen | 2019-05-21 |
| 9412843 | Method for embedded diamond-shaped stress element | Eric C. Harley, Judson R. Holt, Jin Z. Wallner | 2016-08-09 |
| 9236398 | Passive devices for FinFET integrated circuit technologies | William F. Clark, Jr., Robert J. Gauthier, Jr., Terence B. Hook, Junjun Li, Theodorus E. Standaert | 2016-01-12 |
| 9171935 | FinFET formation with late fin reveal | Seong-Dong Kim, Myung-Hee Na, Jin Z. Wallner, Qintao Zhang | 2015-10-27 |
| 8946064 | Transistor with buried silicon germanium for improved proximity control and optimized recess shape | Thomas N. Adam, Judson R. Holt, Alexander Reznicek | 2015-02-03 |
| 8916426 | Passive devices for FinFET integrated circuit technologies | William F. Clark, Jr., Robert J. Gauthier, Jr., Terence B. Hook, Junjun Li, Theodorus E. Standaert | 2014-12-23 |
| 8787074 | Static random access memory test structure | Oliver D. Patterson, Jin Z. Wallner, Shenzhi Yang | 2014-07-22 |
| 8569840 | Bipolar transistor integrated with metal gate CMOS devices | Ebenezer E. Eshun, Daniel Jaeger, Phung T. Nguyen | 2013-10-29 |
| 8232172 | Stress enhanced transistor devices and methods of making | Thomas N. Adam, Judson R. Holt | 2012-07-31 |
| 8129234 | Method of forming bipolar transistor integrated with metal gate CMOS devices | Ebenezer E. Eshun, Daniel Jaeger, Phung T. Nguyen | 2012-03-06 |
| 8124534 | Multiple exposure and single etch integration method | Jin Z. Wallner, Ying Zhang | 2012-02-28 |
| 8062951 | Method to increase effective MOSFET width | Xiangdong Chen, Kenneth J. Stein | 2011-11-22 |
| 7858485 | Structure and method for manufacturing trench capacitance | Huilong Zhu, Babar A. Khan, Xi Li, Joyce C. Liu | 2010-12-28 |
| 7521772 | Monocrystalline extrinsic base and emitter heterojunction bipolar transistor and related methods | Thomas N. Adam | 2009-04-21 |
| 7511317 | Porous silicon for isolation region formation and related structure | Thomas N. Adam, Stephen W. Bedell, Joel P. de Souza, Kathryn T. Schonenberg | 2009-03-31 |
| 7342293 | Bipolar junction transistors (BJTS) with second shallow trench isolation (STI) regions, and methods for forming same | Thomas N. Adam, Stephen W. Bedell, Joel P. de Souza | 2008-03-11 |