Issued Patents All Time
Showing 26–50 of 72 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10303196 | On-chip voltage generator for back-biasing field effect transistors in a circuit block | Navneet Jain, Arif A. Siddiqi | 2019-05-28 |
| 10242946 | Circuit design having aligned power staples | Irene Y. Lin, Lei Yuan | 2019-03-26 |
| 10199378 | Special construct for continuous non-uniform active region FinFET standard cells | Navneet Jain, Juhan Kim, Andy T. Nguyen | 2019-02-05 |
| 10108771 | Method, apparatus and system for forming recolorable standard cells with triple patterned metal layer structures | Juhan Kim | 2018-10-23 |
| 10096595 | Antenna diode circuit for manufacturing of semiconductor devices | Juhan Kim, Navneet Jain, Anurag Mittal, Sangmoon Kim | 2018-10-09 |
| 9893063 | Special construct for continuous non-uniform active region FinFET standard cells | Navneet Jain, Juhan Kim, Andy T. Nguyen | 2018-02-13 |
| 9842184 | Method, apparatus and system for using hybrid library track design for SOI technology | Anurag Mittal | 2017-12-12 |
| 9634003 | Special construct for continuous non-uniform RX FinFET standard cells | Navneet Jain, Juhan Kim, Andy T. Nguyen | 2017-04-25 |
| 9536035 | Wide pin for improved circuit routing | Lei Yuan, Juhan Kim, Jongwook Kye | 2017-01-03 |
| 9530780 | Memory bit cell for reduced layout area | Juhan Kim | 2016-12-27 |
| 9519745 | Method and apparatus for assisted metal routing | Lei Yuan, Irene Y. Lin, Jongwook Kye | 2016-12-13 |
| 9391080 | Memory bit cell for reduced layout area | Juhan Kim | 2016-07-12 |
| 9355910 | Semiconductor device with transistor local interconnects | Irene Y. Lin, Steven R. Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia +3 more | 2016-05-31 |
| 9337099 | Special constructs for continuous non-uniform active region FinFET standard cells | Navneet Jain, Juhan Kim, Andy T. Nguyen | 2016-05-10 |
| 9292647 | Method and apparatus for modified cell architecture and the resulting device | Lei Yuan, Jongwook Kye | 2016-03-22 |
| 9196548 | Methods of using a trench salicide routing layer | Srikanth B. Samavedam, David Doman, Navneet Jain, Subramani Kengeri, Suresh Venkatesan | 2015-11-24 |
| 9159724 | Cross-coupling-based design using diffusion contact structures | Yan Wang, Yuansheng Ma, Jongwook Kye | 2015-10-13 |
| 9147028 | Forming modified cell architecture for finFET technology and resulting device | Lei Yuan | 2015-09-29 |
| 9142513 | Middle-of-the-line constructs using diffusion contact structures | Yuansheng Ma, Irene Y. Lin, Jason E. Stephens, Yunfei Deng, Yuan Lei +5 more | 2015-09-22 |
| 9122830 | Wide pin for improved circuit routing | Lei Yuan, Juhan Kim, Jongwook Kye | 2015-09-01 |
| 9105643 | Bit cell with double patterned metal layer structures | Juhan Kim | 2015-08-11 |
| 9035679 | Standard cell connection for circuit routing | Lei Yuan, Irene Y. Lin, Jongwook Kye | 2015-05-19 |
| 9026977 | Power rail layout for dense standard cell library | Marc Tarabbia, Norman Chen, Jian Liu, Nader Magdy Hindawy, Tuhin Guha Neogi +1 more | 2015-05-05 |
| 9006100 | Middle-of-the-line constructs using diffusion contact structures | Yuansheng Ma, Irene Y. Lin, Jason E. Stephens, Yunfei Deng, Yuan Lei +5 more | 2015-04-14 |
| 8987128 | Cross-coupling based design using diffusion contact structures | Marc Tarabbia, Chinh Nguyen, David Doman, Juhan Kim, Xiang Qi +1 more | 2015-03-24 |