Issued Patents All Time
Showing 51–72 of 72 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8975712 | Densely packed standard cells for integrated circuit products, and methods of making same | Juhan Kim, Yunfei Deng, Suresh Venkatesan | 2015-03-10 |
| 8966423 | Integrating optimal planar and three-dimensional semiconductor design layouts | Navneet Jain, Yunfei Deng, David Doman, Qi Xiang, Jongwook Kye | 2015-02-24 |
| 8916441 | FinFET device and methods of fabrication | Juhan Kim, Yunfei Deng, Jongwook Kye, Suresh Venkatesan | 2014-12-23 |
| 8904324 | Parameterized cell for planar and finFET technology design | Navneet Jain, Paul D. Mesa, Qinglei Wang, Qi Xiang | 2014-12-02 |
| 8881083 | Methods for improving double patterning route efficiency | Yunfei Deng, Lei Yuan, Hidekazu Yoshida, Juhan Kim, Jongwook Kye | 2014-11-04 |
| 8859416 | Software and method for via spacing in a semiconductor device | David Doman, Marc Tarrabia | 2014-10-14 |
| 8823178 | Bit cell with double patterned metal layer structures | Juhan Kim | 2014-09-02 |
| 8789000 | Variable power rail design | Lei Yuan, Jongwook Kye, Suresh Venkatesan | 2014-07-22 |
| 8741763 | Layout designs with via routing structures | Yuansheng Ma, Jongwook Kye, Harry J. Levinson, Hidekazu Yoshida | 2014-06-03 |
| 8735050 | Integrated circuits and methods for fabricating integrated circuits using double patterning processes | Lei Yuan, Hidekazu Yoshida, Jongwook Kye, Qi Xiang | 2014-05-27 |
| 8689154 | Providing timing-closed FinFET designs from planar designs | David Doman, Dinesh Somasekhar, Yan Wang, Yunfei Deng, Navneet Jain +4 more | 2014-04-01 |
| 8679911 | Cross-coupling-based design using diffusion contact structures | Yan Wang, Yuansheng Ma, Jongwook Kye | 2014-03-25 |
| 8677291 | Double patterning compatible colorless M1 route | Lei Yuan, Jongwook Kye, Qinglei Wang | 2014-03-18 |
| 8618607 | Semiconductor devices formed on a continuous active region with an isolating conductive structure positioned between such semiconductor devices, and methods of making same | David Doman, Marc Tarabbia, Irene Y. Lin, Jeff Kim, Chinh Nguyen +4 more | 2013-12-31 |
| 8598633 | Semiconductor device having contact layer providing electrical connections | Marc Tarabbia, James B. Gullette, David Doman, Irene Y. Lin, Ingolf Lorenz +12 more | 2013-12-03 |
| 8581348 | Semiconductor device with transistor local interconnects | Steven R. Soss, Jongwook Kye, Irene Y. Lin, James B. Gullette, Chinh Nguyen +9 more | 2013-11-12 |
| 7867858 | Hybrid transistor based power gating switch circuit and method | Giri Nallapati, Sushama Davar, Robert E. Booth, Michael P. Woo | 2011-01-11 |
| 7741195 | Method of stimulating die circuitry and structure therefor | Mohammed Rashid, Scott S. Roth | 2010-06-22 |
| 7612577 | Speedpath repair in an integrated circuit | Milind P. Padhye | 2009-11-03 |
| 7542360 | Programmable bias for a memory array | Robert E. Booth, Sushama Davar, Giri Nallapati | 2009-06-02 |
| 7274247 | System, method and program product for well-bias set point adjustment | Gregory Hall Ward, Mohamed S. Moosa | 2007-09-25 |
| 7138842 | Flip-flop circuit having low power data retention | Milind P. Padhye, Yuan Yuan | 2006-11-21 |