Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7867858 | Hybrid transistor based power gating switch circuit and method | Giri Nallapati, Sushama Davar, Robert E. Booth, Mahbub Rashed | 2011-01-11 |
| 6686633 | Semiconductor device, memory cell, and processes for forming them | Craig S. Lage, Mousumi Bhat, Yeong-Jyh T. Lii, Andrew G. Nagy, Larry E. Frisa +5 more | 2004-02-03 |
| 6440805 | Method of forming a semiconductor device with isolation and well regions | Xiaodong Wang, Craig S. Lage, Hong Tian | 2002-08-27 |
| 6291888 | Contact structure and process for formation | Mousumi Bhat, Mark D. Hall, Arkalgud R. Sitaram | 2001-09-18 |
| 6184073 | Process for forming a semiconductor device having an interconnect or conductive film electrically insulated from a conductive member or region | Craig S. Lage, Mousumi Bhat, Yeong-Jyh T. Lii, Andrew G. Nagy, Larry E. Frisa +5 more | 2001-02-06 |
| 6037246 | Method of making a contact structure | Mousumi Bhat, Mark D. Hall, Arkalgud R. Sitaram | 2000-03-14 |
| 5621233 | Electrically programmable read-only memory cell | Umesh Sharma | 1997-04-15 |
| 5498560 | Process for forming an electrically programmable read-only memory cell | Umesh Sharma | 1996-03-12 |
| 5451543 | Straight sidewall profile contact opening to underlying interconnect and method for making the same | Robert Chebi, James D. Hayden | 1995-09-19 |
| 5408130 | Interconnection structure for conductive layers | James D. Hayden, Richard D. Sivan, Howard C. Kirsch, Bich-Yen Nguyen | 1995-04-18 |
| 5405806 | Method for forming a metal silicide interconnect in an integrated circuit | James R. Pfiester, James D. Hayden | 1995-04-11 |
| 5381040 | Small geometry contact | Shih-Wei Sun | 1995-01-10 |
| 5279990 | Method of making a small geometry contact using sidewall spacers | Shih-Wei Sun | 1994-01-18 |
| 5262352 | Method for forming an interconnection structure for conductive layers | James D. Hayden, Richard D. Sivan, Howard C. Kirsch, Bich-Yen Nguyen | 1993-11-16 |
| 5210435 | ITLDD transistor having a variable work function | Scott S. Roth, Carlos Mazure, Kent J. Cooper, Wayne J. Ray, Jung-Hui Lin | 1993-05-11 |
| 5158910 | Process for forming a contact structure | Kent J. Cooper, Wayne J. Ray | 1992-10-27 |
| 5061647 | ITLDD transistor having variable work function and method for fabricating the same | Scott S. Roth, Carlos Mazure, Kent J. Cooper, Wayne J. Ray, Jung-Hui Lin | 1991-10-29 |
| 5037777 | Method for forming a multi-layer semiconductor device using selective planarization | Thomas C. Mele, Wayne M. Paulson, Frank K. Baker, Jr. | 1991-08-06 |
| 5034351 | Process for forming a feature on a substrate without recessing the surface of the substrate | Shih-Wei Sun | 1991-07-23 |
| 4997790 | Process for forming a self-aligned contact structure | Thomas C. Mele, Wayne J. Ray, Wayne M. Paulson | 1991-03-05 |
| 4897364 | Method for locos isolation using a framed oxidation mask and a polysilicon buffer layer | Bich-Yen Nguyen, Philip J. Tobin, Shih-Wei Sun | 1990-01-30 |