Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5541132 | Insulated gate semiconductor device and method of manufacture | Robert B. Davies, Vida Ilderem, Mark Griswold, Diann Dow, James E. Prendergast +4 more | 1996-07-30 |
| 5408130 | Interconnection structure for conductive layers | Michael P. Woo, James D. Hayden, Howard C. Kirsch, Bich-Yen Nguyen | 1995-04-18 |
| 5358890 | Process for fabricating isolation regions in a semiconductor device | James R. Pfiester | 1994-10-25 |
| 5324973 | Semiconductor SRAM with trench transistors | — | 1994-06-28 |
| 5285093 | Semiconductor memory cell having a trench structure | Craig S. Lage | 1994-02-08 |
| 5262352 | Method for forming an interconnection structure for conductive layers | Michael P. Woo, James D. Hayden, Howard C. Kirsch, Bich-Yen Nguyen | 1993-11-16 |
| 5244824 | Trench capacitor and transistor structure and method for making the same | — | 1993-09-14 |
| 5229310 | Method for making a self-aligned vertical thin-film transistor in a semiconductor device | — | 1993-07-20 |
| 5198683 | Integrated circuit memory device and structural layout thereof | — | 1993-03-30 |
| 5082794 | Method of fabricating MOS transistors using selective polysilicon deposition | James R. Pfiester, Frank K. Baker, Jr. | 1992-01-21 |
| 5061646 | Method for forming a self-aligned bipolar transistor | James D. Hayden | 1991-10-29 |
| 5006911 | Transistor device with high density contacts | — | 1991-04-09 |
| 4984042 | MOS transistors using selective polysilicon deposition | James R. Pfiester, Frank K. Baker, Jr. | 1991-01-08 |
| 4948745 | Process for elevated source/drain field effect structure | James R. Pfiester | 1990-08-14 |
| 4942137 | Self-aligned trench with selective trench fill | James R. Pfiester, John E. Leiss | 1990-07-17 |