Issued Patents All Time
Showing 1–25 of 69 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8358548 | Methods for efficiently repairing embedded dynamic random-access memory having marginally failing cells | Indrajit Manna, David Leary | 2013-01-22 |
| 7280002 | Method and apparatus for biasing a metal-oxide-semiconductor capacitor for capacitive tuning | Alvin Leng Sun Loke, Tin Tin Wee, Robert Keith Barnes, Kari Lee Arave, Thomas E. Cynkar | 2007-10-09 |
| 5616948 | Semiconductor device having electrically coupled transistors with a differential current gain | — | 1997-04-01 |
| 5536962 | Semiconductor device having a buried channel transistor | — | 1996-07-16 |
| 5473185 | Static-random-access memory cell with channel stops having differing doping concentrations | James D. Hayden | 1995-12-05 |
| 5459688 | Semiconductor memory cell and fabrication process | James D. Hayden | 1995-10-17 |
| 5426315 | Thin-film transistor having an inlaid thin-film channel region | — | 1995-06-20 |
| 5422300 | Method for forming electrical isolation in an integrated circuit | Prashant U. Kenkare, Kent J. Cooper, Bich-Yen Nguyen | 1995-06-06 |
| 5413948 | Method for forming a dual transistor structure | James D. Hayden | 1995-05-09 |
| 5407847 | Method for fabricating a semiconductor device having a shallow doped region | James D. Hayden, David Burnett | 1995-04-18 |
| 5405806 | Method for forming a metal silicide interconnect in an integrated circuit | James D. Hayden, Michael P. Woo | 1995-04-11 |
| 5393689 | Process for forming a static-random-access memory cell | James D. Hayden | 1995-02-28 |
| 5373170 | Semiconductor memory device having a compact symmetrical layout | James D. Hayden | 1994-12-13 |
| 5371035 | Method for forming electrical isolation in an integrated circuit device | Philip J. Tobin | 1994-12-06 |
| 5371026 | Method for fabricating paired MOS transistors having a current-gain differential | James D. Hayden, Hsing-Huang Tseng | 1994-12-06 |
| 5369052 | Method of forming dual field oxide isolation | Prashant U. Kenkare, Shih-Wei Sun | 1994-11-29 |
| 5358890 | Process for fabricating isolation regions in a semiconductor device | Richard D. Sivan | 1994-10-25 |
| 5352631 | Method for forming a transistor having silicided regions | Arkalgud R. Sitaram | 1994-10-04 |
| 5348903 | Process for fabricating a semiconductor memory cell having thin-film driver transistors overlapping dual wordlines | James D. Hayden | 1994-09-20 |
| 5334861 | Semiconductor memory cell | James D. Hayden | 1994-08-02 |
| 5330929 | Method of making a six transistor static random access memory cell | James D. Hayden | 1994-07-19 |
| 5324960 | Dual-transistor structure and method of formation | James D. Hayden | 1994-06-28 |
| 5319232 | Transistor having a lightly doped region | — | 1994-06-07 |
| 5291053 | Semiconductor device having an overlapping memory cell | James D. Hayden | 1994-03-01 |
| 5279976 | Method for fabricating a semiconductor device having a shallow doped region | James D. Hayden, David Burnett | 1994-01-18 |