Issued Patents All Time
Showing 51–69 of 69 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 4942137 | Self-aligned trench with selective trench fill | Richard D. Sivan, John E. Leiss | 1990-07-17 |
| 4928156 | N-channel MOS transistors having source/drain regions with germanium | John R. Alvis, Orin W. Holland | 1990-05-22 |
| 4918510 | Compact CMOS device structure | — | 1990-04-17 |
| 4876213 | Salicided source/drain structure | — | 1989-10-24 |
| 4852062 | EPROM device using asymmetrical transistor characteristics | Frank K. Baker, Jr., Charles Frederick Hart | 1989-07-25 |
| 4847213 | Process for providing isolation between CMOS devices | — | 1989-07-11 |
| 4837173 | N-channel MOS transistors having source/drain regions with germanium | John R. Alvis, Orin W. Holland | 1989-06-06 |
| 4835112 | CMOS salicide process using germanium implantation | John R. Yeargain | 1989-05-30 |
| 4835589 | Ram cell having trench sidewall load | — | 1989-05-30 |
| 4812418 | Micron and submicron patterning without using a lithographic mask having submicron dimensions | Louis C. Parrillo, J. William Dockrey | 1989-03-14 |
| 4811066 | Compact multi-state ROM cell | Frank K. Baker, Jr. | 1989-03-07 |
| 4786611 | Adjusting threshold voltages by diffusion through refractory metal silicides | — | 1988-11-22 |
| 4761385 | Forming a trench capacitor | — | 1988-08-02 |
| 4745079 | Method for fabricating MOS transistors having gates with different work functions | — | 1988-05-17 |
| 4743563 | Process of controlling surface doping | John R. Alvis, Orin W. Holland | 1988-05-10 |
| 4728619 | Field implant process for CMOS using germanium | John R. Alvis, Orin W. Holland | 1988-03-01 |
| 4714519 | Method for fabricating MOS transistors having gates with different work functions | — | 1987-12-22 |
| 4318014 | Selective precharge circuit for read-only-memory | Doyle V. McAlister | 1982-03-02 |
| 4292547 | IGFET Decode circuit using series-coupled transistors | Doyle V. McAlister | 1981-09-29 |