Issued Patents All Time
Showing 1–25 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10529778 | Vertical cross-point memory arrays | Lidia Vereen, Bruce L. Bateman, David Eggleston | 2020-01-07 |
| 10448763 | Systems and methods for a frame hanging device | — | 2019-10-22 |
| 10050086 | Vertical cross-point memory arrays | Lidia Vereen, Bruce L. Bateman, David Eggleston | 2018-08-14 |
| 9549624 | Systems and methods for a frame hanging device | — | 2017-01-24 |
| 9419217 | Vertical cross-point memory arrays | Lidia Vereen, Bruce L. Bateman, David Eggleston | 2016-08-16 |
| 9029827 | Planar resistive memory integration | Lidia Vereen, Bruce L. Bateman, Elizabeth Friend, David Eggleston | 2015-05-12 |
| 8610099 | Planar resistive memory integration | Lidia Vereen, Bruce L. Bateman, Elizabeth Friend, David Eggleston | 2013-12-17 |
| 5527739 | Process for fabricating a semiconductor device having an improved metal interconnect structure | Jeffrey L. Klein | 1996-06-18 |
| 5442553 | Wireless motor vehicle diagnostic and software upgrade system | — | 1995-08-15 |
| 5442235 | Semiconductor device having an improved metal interconnect structure | Jeffrey L. Klein | 1995-08-15 |
| 5208168 | Semiconductor device having punch-through protected buried contacts and method for making the same | Neil B. Henis, Richard W. Mauntel | 1993-05-04 |
| 4951100 | Hot electron collector for a LDD transistor | — | 1990-08-21 |
| 4929565 | High/low doping profile for twin well process | — | 1990-05-29 |
| 4889825 | High/low doping profile for twin well process | — | 1989-12-26 |
| 4812418 | Micron and submicron patterning without using a lithographic mask having submicron dimensions | James R. Pfiester, J. William Dockrey | 1989-03-14 |
| 4808543 | Well Extensions for trench devices | Richard W. Mauntel, John M. Barden | 1989-02-28 |
| 4808555 | Multiple step formation of conductive material layers | Richard W. Mauntel, Stephen J. Cosentino, Patrick J. Holly | 1989-02-28 |
| 4801555 | Double-implant process for forming graded source/drain regions | Patrick J. Holly, Frank K. Baker, Jr. | 1989-01-31 |
| 4769747 | Illuminated paper cutter | — | 1988-09-06 |
| 4766090 | Methods for fabricating latchup-preventing CMOS device | Gerald A. Coquin, William T. Lynch | 1988-08-23 |
| 4762802 | Method for preventing latchup in CMOS devices | — | 1988-08-09 |
| 4753898 | LDD CMOS process | Stephen S. Poon | 1988-06-28 |
| 4745086 | Removable sidewall spacer for lightly doped drain formation using one mask level and differential oxidation | Stephen J. Cosentino, Richard W. Mauntel | 1988-05-17 |
| 4722909 | Removable sidewall spacer for lightly doped drain formation using two mask levels | Stephen J. Cosentino, Richard W. Mauntel | 1988-02-02 |
| 4717683 | CMOS process | Stephen J. Cosentino, Bridgette A. Bergami | 1988-01-05 |