Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11036913 | Integrated circuit methods using single-pin imaginary devices | Heng Lan Lau, Manjunatha Prabhu, Shawn Walsh | 2021-06-15 |
| 10796973 | Test structures connected with the lowest metallization levels in an interconnect structure | Mankyu Yang, Vara Govindeswara Reddy Vakada, Edward P. Maciejewski, Brian J. Greene, Atsushi Ogino +1 more | 2020-10-06 |
| 10790204 | Test structure leveraging the lowest metallization level of an interconnect structure | Mankyu Yang, Vara Govindeswara Reddy Vakada, Edward P. Maciejewski, Brian J. Greene, Atsushi Ogino +1 more | 2020-09-29 |
| 10579774 | Integrated circuit (IC) design systems and methods using single-pin imaginary devices | Heng Lan Lau, Manjunatha Prabhu, Shawn Walsh | 2020-03-03 |
| 10347543 | FDSOI semiconductor device with contact enhancement layer and method of manufacturing | Peter Baars, Rick Carter, George Jonathan Kluth, Anurag Mittal, David Pritchard +1 more | 2019-07-09 |
| 10311186 | Three-dimensional pattern risk scoring | Jaime Bravo, Piyush Pathak, Shobhit Malik, Uwe Schroeder | 2019-06-04 |
| 10236350 | Method, apparatus and system for a high density middle of line flow | Guillaume Bouche, Tuhin Guha Neogi, Sudharshanan Raghunathan, Andy Chi-Hung Wei, Jason E. Stephens +1 more | 2019-03-19 |
| 10199270 | Multi-directional self-aligned multiple patterning | Colin Bombardier, Ming He, Anbu Selvam KM Mahalingam, Keith Donegan | 2019-02-05 |
| 10147783 | On-chip capacitors with floating islands | Atsushi Ogino, Kong Boon Yeap, Ahmed Hassan | 2018-12-04 |
| 10078107 | Wafer level electrical test for optical proximity correction and/or etch bias | Jaime Bravo, Ryan Smith | 2018-09-18 |
| 9465907 | Multi-polygon constraint decomposition techniques for use in double patterning applications | Ahmed Hassan, Nader Magdy Hindawy, Jason E. Stephens, David Pritchard, Abbas Guvenilir +2 more | 2016-10-11 |
| 9412655 | Forming merged lines in a metallization layer by replacing sacrificial lines with conductive lines | Guillaume Bouche, Jason E. Stephens, Andy Wei | 2016-08-09 |
| 8932961 | Critical dimension and pattern recognition structures for devices manufactured using double patterning techniques | Sohan S. Mehta, Tong Qing Chen, Ravi Prakash Srivastava, Catherine B. Labelle, Mark Kelling | 2015-01-13 |
| 8856715 | Capacitor designs for integrated circuits utilizing self-aligned double patterning (SADP) | Jason E. Stephens, Lawrence A. Clevenger, Ning Lu, Albert M. Chu | 2014-10-07 |