Issued Patents All Time
Showing 25 most recent of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7273787 | Method for manufacturing gate dielectric layer | Wen-Ji Chen, Kai-An Hsueh, Sheng-Hone Zheng | 2007-09-25 |
| 7074674 | Method for manufacturing one-time electrically programmable read only memory | Ko-Hsing Chang, Tung-Ming Lai, Chen-Chiu Hsue | 2006-07-11 |
| 6670249 | Process for forming high temperature stable self-aligned metal silicide layer | Hong-Tsz Pan | 2003-12-30 |
| 6426256 | Method for fabricating an embedded DRAM with self-aligned borderless contacts | — | 2002-07-30 |
| 6350646 | Method for reducing thermal budget in node contact application | Yung-Chang Lin | 2002-02-26 |
| 6316311 | Method of forming borderless contact | Tong-Yu Chen, Keh-Ching Huang, Jacob Chen | 2001-11-13 |
| 6316321 | Method for forming MOSFET | Yung-Chang Lin, Jih-Wen Chou | 2001-11-13 |
| 6297112 | Method of forming a MOS transistor | Tony Lin, Ming-Yin Hao | 2001-10-02 |
| 6277721 | Salicide formation process | Hong-Tsz Pan, Wen-Yi Hsieh | 2001-08-21 |
| 6255152 | Method of fabricating CMOS using Si-B layer to form source/drain extension junction | — | 2001-07-03 |
| 6228730 | Method of fabricating field effect transistor | Jih-Wen Chou | 2001-05-08 |
| 6225155 | Method of forming salicide in embedded dynamic random access memory | Yung-Chang Lin, Jacob Chen | 2001-05-01 |
| 6197672 | Method for forming polycide dual gate | Yung-Chang Lin, Jacob Chen | 2001-03-06 |
| 6187674 | Manufacturing method capable of preventing corrosion and contamination of MOS gate | Yung-Chang Lin, Keh-Ching Huang, Jacob Chen | 2001-02-13 |
| 6187644 | Method of removing oxynitride by forming an offset spacer | Tony Lin | 2001-02-13 |
| 6177334 | Manufacturing method capable of preventing corrosion of metal oxide semiconductor | Yung-Chang Lin, Jacob Chen | 2001-01-23 |
| 6156126 | Method for reducing or avoiding the formation of a silicon recess in SDE junction regions | Jih-Wen Chou | 2000-12-05 |
| 6156633 | Process for forming high temperature stable self-aligned metal silicide layer | Hong-Tsz Pan | 2000-12-05 |
| 6153520 | Method for fabricating self-aligned silicide | — | 2000-11-28 |
| 6150205 | Method of fabricating dual gate | Yung-Chang Lin | 2000-11-21 |
| 6133130 | Method for fabricating an embedded dynamic random access memory using self-aligned silicide technology | Yung-Chang Lin, Jacob Chen | 2000-10-17 |
| 6124621 | Structure of a spacer | Yung-Chang Lin, Jih-Wen Chou | 2000-09-26 |
| 6060349 | Planarization on an embedded dynamic random access memory | Tzu-Min Peng, Keh-Ching Huang, Tz-Guei Jung | 2000-05-09 |
| 6022795 | Salicide formation process | Hong-Tsz Pan, Wen-Yi Hsieh | 2000-02-08 |
| 6010958 | Method for improving the planarization of dielectric layer in the fabrication of metallic interconnects | Bing Wu, Hong-Tsz Pan | 2000-01-04 |