Issued Patents All Time
Showing 26–50 of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6232244 | Methodology for achieving dual gate oxide thicknesses | — | 2001-05-15 |
| 6228746 | Methodology for achieving dual field oxide thicknesses | — | 2001-05-08 |
| 6229198 | Non-uniform gate doping for reduced overlap capacitance | Carl Robert Huster | 2001-05-08 |
| 6225170 | Self-aligned damascene gate with contact formation | Richard P. Rouse | 2001-05-01 |
| 6207542 | Method for establishing ultra-thin gate insulator using oxidized nitride film | — | 2001-03-27 |
| 6204157 | Method for establishing shallow junction in semiconductor device to minimize junction capacitance | — | 2001-03-20 |
| 6180466 | Isotropic assisted dual trench etch | — | 2001-01-30 |
| 6177312 | Method for removing contaminate nitrogen from the peripheral gate region of a non-volatile memory device during production of such device | Yuesong He, John Jianshi Wang, Toru Ishigaki, Kent Kuohua Chang | 2001-01-23 |
| 6171962 | Shallow trench isolation formation without planarization mask | Olov Karlsson, Christopher F. Lyons, Basab Bandyopadhyay, Nick Kepler, Larry Wang | 2001-01-09 |
| 6165877 | Method for establishing shallow junction in semiconductor device to minimize junction capacitance | — | 2000-12-26 |
| 6162699 | Method for generating limited isolation trench width structures and a device having a narrow isolation trench surrounding its periphery | Larry Wang, Nick Kepler, Olov Karlsson, Basab Bandyopadhyay, Christopher F. Lyons | 2000-12-19 |
| 6153486 | Method for establishing shallow junction in semiconductor device to minimize junction capacitance | — | 2000-11-28 |
| 6143624 | Shallow trench isolation formation with spacer-assisted ion implantation | Nick Kepler, Olov Karlsson, Larry Wang, Basab Bandyopadhyay, Christopher F. Lyons | 2000-11-07 |
| 6130467 | Shallow trench isolation with spacers for improved gate oxide quality | Basab Bandyopadhyay, Nick Kepler, Olov Karlsson, Larry Wang, Christopher F. Lyons | 2000-10-10 |
| 6124183 | Shallow trench isolation formation with simplified reverse planarization mask | Olov Karlsson, Christopher F. Lyons, Basab Bandyopadhyay, Nick Kepler, Larry Wang | 2000-09-26 |
| 6090713 | Shallow trench isolation formation with simplified reverse planarization mask | Olov Karlsson, Christopher F. Lyons, Basab Bandyophadhyay, Nick Kepler, Larry Wang | 2000-07-18 |
| 6080682 | Methodology for achieving dual gate oxide thicknesses | — | 2000-06-27 |
| 6074927 | Shallow trench isolation formation with trench wall spacer | Nick Kepler, Basab Bandyopadhyay, Olov Karlsson, Larry Wang, Christopher F. Lyons | 2000-06-13 |
| 6051478 | Method of enhancing trench edge oxide quality | — | 2000-04-18 |
| 6043138 | Multi-step polysilicon deposition process for boron penetration inhibition | — | 2000-03-28 |
| 6037671 | Stepper alignment mark structure for maintaining alignment integrity | Nick Kepler, Olov Karlsson, Larry Wang, Basab Bandyopadhyay, Christopher F. Lyons | 2000-03-14 |
| 6034395 | Semiconductor device having a reduced height floating gate | Nicholas H. Tripsas, Tuan Pham | 2000-03-07 |
| 6025228 | Method of fabricating an oxynitride-capped high dielectric constant interpolysilicon dielectric structure for a low voltage non-volatile memory | Yue-Song He | 2000-02-15 |
| 6020238 | Method of fabricating a high dielectric constant interpolysilicon dielectric structure for a low voltage non-volatile memory | Yue-Song He | 2000-02-01 |
| 5970362 | Simplified shallow trench isolation formation with no polish stop | Christopher F. Lyons, Basab Bandyopadhyay, Nick Kepler, Olov Karlsson, Larry Wang | 1999-10-19 |