Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6524916 | Controlled gate length and gate profile semiconductor device and manufacturing method therefor | Allen S. Yu, Paul J. Steffan | 2003-02-25 |
| 6448606 | Semiconductor with increased gate coupling coefficient | Allen S. Yu, Paul J. Steffan | 2002-09-10 |
| 6433371 | Controlled gate length and gate profile semiconductor device | Allen S. Yu, Paul J. Steffan | 2002-08-13 |
| 6287968 | Method of defining copper seed layer for selective electroless plating processing | Allen S. Yu, Paul J. Steffan | 2001-09-11 |
| 6239008 | Method of making a density multiplier for semiconductor device manufacturing | Allen S. Yu, Paul J. Steffan | 2001-05-29 |
| 6133140 | Method of manufacturing dual damascene utilizing anisotropic and isotropic properties | Allen S. Yu, Paul J. Steffan | 2000-10-17 |
| 6107204 | Method to manufacture multiple damascene by utilizing etch selectivity | Allen S. Yu, Paul J. Steffan | 2000-08-22 |
| 6103616 | Method to manufacture dual damascene structures by utilizing short resist spacers | Allen S. Yu, Paul J. Steffan | 2000-08-15 |
| 6100593 | Multiple chip hybrid package using bump technology | Allen S. Yu, Paul J. Steffan | 2000-08-08 |
| 6091138 | Multi-chip packaging using bump technology | Allen S. Yu, Paul J. Steffan | 2000-07-18 |
| 6025272 | Method of planarize and improve the effectiveness of the stop layer | Allen S. Yu, Paul J. Steffan | 2000-02-15 |
| 6025259 | Dual damascene process using high selectivity boundary layers | Allen S. Yu, Paul J. Steffan | 2000-02-15 |
| 5985753 | Method to manufacture dual damascene using a phantom implant mask | Allen S. Yu, Paul J. Steffan | 1999-11-16 |