Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Test structure and method for failure analysis of small contacts in integrated circuit technology development

Test structure and method for failure analysis of small contacts in integrated circuit technology development

US Patent 7135879 · Granted Nov 14, 2006

Estimated economic value: $38,989,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Image processing in integrated circuit technology development2009
Method and apparatus for correlating semiconductor process data with known prior2007
Predicting defect future effects in integrated circuit technology development to2007
Wafer level global bitmap characterization in integrated circuit technology deve2006
Wafer level global bitmap characterization in integrated circuit technology deve2006
Characterizing distribution signatures in integrated circuit technology2006
Testing multiple levels in integrated circuit technology development2005
Methods to form reduced dimension bit-line isolation in the manufacture of non-v2003
Controlled gate length and gate profile semiconductor device and manufacturing m2003
Composition based association engine for image archival systems2003
Method of forming low resistance reduced channel length transistors2003
Overlay radius offset shift engine2002