Issued Patents All Time
Showing 51–75 of 157 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7704878 | Contact spacer formation using atomic layer deposition | Minh Van Ngo, Amol Joshi, Wenmei Li, Ning Cheng, Ankur Agarwal +1 more | 2010-04-27 |
| 7696038 | Methods for fabricating flash memory devices | Ning Cheng, Kuo-Tung Chang, Hiroyuki Kinoshita, Timothy Thurgate, Wei Zheng +2 more | 2010-04-13 |
| 7691751 | Selective silicide formation using resist etchback | Kyunghoon Min, Hiroyuki Kinoshita, Ning Cheng, Mark S. Chang | 2010-04-06 |
| 7679129 | System and method for improving oxide-nitride-oxide (ONO) coupling in a semiconductor device | Unsoon Kim, Hiroyuki Kinoshita, Kuo-Tung Chang | 2010-03-16 |
| 7670959 | Memory device etch methods | Jihwan P. Choi | 2010-03-02 |
| 7622389 | Selective contact formation using masking and resist patterning techniques | Kyunghoon Min, Mark S. Chang, Ning Cheng, Brian Osborn, Kevin Song +3 more | 2009-11-24 |
| 7572727 | Semiconductor formation method that utilizes multiple etch stop layers | Wenmei Li, Dawn Hopper, Kouros Ghandehari | 2009-08-11 |
| 7432178 | Bit line implant | Jean Y. Yang, Yu Sun, Mark T. Ramsbey, Weidong Qian | 2008-10-07 |
| 7361587 | Semiconductor contact and nitride spacer formation system and method | Wenmei Li, Dawn Hopper, Kouros Ghandehari | 2008-04-22 |
| 7341956 | Disposable hard mask for forming bit lines | Hirokazu Tokuno, Minh Van Ngo, Cinti X. Chen | 2008-03-11 |
| 7323418 | Etch-back process for capping a polymer memory device | Minh Van Ngo, Sergey Lopatin | 2008-01-29 |
| 7300886 | Interlayer dielectric for charge loss improvement | Minh Van Ngo, Ning Cheng, Wenmei Li, Pei-Yuan Gao, Robert A. Huertas | 2007-11-27 |
| 7301193 | Structure and method for low Vss resistance and reduced DIBL in a floating gate memory cell | Shenqing Fang, Timothy Thurgate, Kuo-Tung Chang, Richard Fastow, Kazuhiro Mizutani +4 more | 2007-11-27 |
| 7285499 | Polymer spacers for creating sub-lithographic spaces | Scott A. Bell, Phillip Jones | 2007-10-23 |
| 7265014 | Avoiding field oxide gouging in shallow trench isolation (STI) regions | Jusuke Ogura, Yider Wu | 2007-09-04 |
| 7238571 | Non-volatile memory device with increased reliability | Hirokazu Tokuno, Wenmei Li, Ning Cheng, Minh Van Ngo, Cinti X. Chen | 2007-07-03 |
| 7157335 | Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact resistance in multi bit memory devices | Ning Cheng, Minh Van Ngo, Hirokazu Tokuno, Lu You, Yi He +3 more | 2007-01-02 |
| 7115440 | SO2 treatment of oxidized CuO for copper sulfide formation of memory element growth | Christopher F. Lyons, Ramkumar Subramanian, Sergey Lopatin, James J. Xie | 2006-10-03 |
| 7067388 | Flash memory device and method of forming the same with improved gate breakdown and endurance | Yider Wu | 2006-06-27 |
| 7023046 | Undoped oxide liner/BPSG for improved data retention | Minh Van Ngo, Ning Cheng, Jeyong Park, Jean Y. Yang, Robert A. Huertas +3 more | 2006-04-04 |
| 7018896 | UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL processing | Minh Van Ngo, Tazrien Kamal, Mark T. Ramsbey, Arvind Halliyal, Jaeyong Park +6 more | 2006-03-28 |
| 7015135 | Method and system for reducing contact defects using non conventional contact formation method for semiconductor cells | Wenmei Li, Amy C. Tu | 2006-03-21 |
| 7015134 | Method for reducing anti-reflective coating layer removal during removal of photoresist | Marina V. Plat | 2006-03-21 |
| 7012008 | Dual spacer process for non-volatile memory devices | Jeffrey A. Shields, Tuan Pham, Mark T. Ramsbey, Yu Sun, Maria C. Chan | 2006-03-14 |
| 6974995 | Method and system for forming dual gate structures in a nonvolatile memory using a protective layer | Shenqing Fang, Hiroyuki Kinoshita, Kelwin Ko, Wenmei Li, Yu Sun +2 more | 2005-12-13 |