JO

Jusuke Ogura

AM AMD: 11 patents #1,098 of 9,279Top 15%
Fujitsu Limited: 9 patents #3,538 of 24,456Top 15%
FL Fujitsu Semiconductor Limited: 9 patents #48 of 1,301Top 4%
SL Spansion Llc.: 3 patents #241 of 769Top 35%
FA Fasl: 1 patents #23 of 52Top 45%
Overall (All Time): #174,223 of 4,157,543Top 5%
24
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
9287168 Semiconductor device and process for producing the same Hiroshi Morioka, Sergey Pidin 2016-03-15
8884375 Semiconductor integrated circuit device Satoshi Nakai, Masato Suga 2014-11-11
8790974 Method of manufacturing semiconductor integrated circuit device Satoshi Nakai, Masato Suga 2014-07-29
8749062 Semiconductor device and process for producing the same Hiroshi Morioka, Sergey Pidin 2014-06-10
8518795 Method of manufacturing semiconductor device Hikaru Kokura, Hideyuki Kojima, Toru Anezaki, Hiroyuki Ogawa, Junichi Ariyoshi 2013-08-27
8368219 Buried silicide local interconnect with sidewall spacers and method for making the same Arvind Halliyal, Zoran Krivokapic, Matthew S. Buynoski, Nicholas H. Tripsas, Minh Van Ngo +2 more 2013-02-05
8362569 Semiconductor device and semiconductor device fabrication method Tomoyuki Kirimura 2013-01-29
8173514 Method of manufacturing semiconductor device Hikaru Kokura, Hideyuki Kojima, Toru Anezaki, Hiroyuki Ogawa, Junichi Ariyoshi 2012-05-08
8049334 Buried silicide local interconnect with sidewall spacers and method for making the same Arvind Halliyal, Zoran Krivokapic, Matthew S. Buynoski, Nicholas H. Tripsas, Minh Van Ngo +2 more 2011-11-01
7892969 Method of manufacturing semiconductor device Masanori Tsutsumi 2011-02-22
7816206 Semiconductor device and method for fabricating the same 2010-10-19
7786003 Buried silicide local interconnect with sidewall spacers and method for making the same Arvind Halliyal, Zoran Krivokapic, Matthew S. Buynoski, Nicholas H. Tripsas, Minh Van Ngo +2 more 2010-08-31
7265014 Avoiding field oxide gouging in shallow trench isolation (STI) regions Angela T. Hui, Yider Wu 2007-09-04
7199426 Nonvolatile semiconductor memory device and method for fabricating the same Hiroyuki Ogawa, Tatsuo Chijimatsu 2007-04-03
6828199 Monos device having buried metal silicide bit line Mark T. Ramsbey, Arvind Halliyal, Zoran Krivokapic, Minh Van Ngo, Nicholas H. Tripisas 2004-12-07
6809033 Innovative method of hard mask removal Angela T. Hui 2004-10-26
6713809 Dual bit memory device with isolated polysilicon floating gates Kazuhiro Kurihara, Masaru Yano, Hideki Komori, Tuan Pham, Angela T. Hui 2004-03-30
6642148 RELACS shrink method applied for single print resist mask for LDD or buried bitline implants using chemically amplified DUV type photoresist Kouros Ghandehari, Emmanuil H. Lingunis, Mark S. Chang, Angela T. Hui, Scott A. Bell 2003-11-04
6617215 Memory wordline hard mask Arvind Halliyal, Tazrien Kamal, Minh Van Ngo, Mark T. Ramsbey, Jeffrey A. Shields +3 more 2003-09-09
6573140 Process for making a dual bit memory device with isolated polysilicon floating gates Kiyoshi Izumi, Masaru Yano, Hideki Komori, Tuan Pham, Angela T. Hui 2003-06-03
6537866 Method of forming narrow insulating spacers for use in reducing minimum component size Jeffrey A. Shields, Tuan Pham, Bharath Rangarajan, Simon S. Chan 2003-03-25
6479411 Method for forming high quality multiple thickness oxide using high temperature descum Angela T. Hui 2002-11-12
6461973 Method for forming high quality multiple thickness oxide layers by reducing descum induced defects Angela T. Hui 2002-10-08
6432618 Method for forming high quality multiple thickness oxide layers by reducing descum induced defects Angela T. Hui 2002-08-13