Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8862851 | Architecture for address mapping of managed non-volatile memory | Tahoma M. Toelkes, Nir Jacob Wakrat, Kenneth Louis Herman, Barry Corlett, Vadim Khmelnitsky +2 more | 2014-10-14 |
| 8832507 | Systems and methods for generating dynamic super blocks | Daniel J. Post | 2014-09-09 |
| 8658496 | Etch stop layer for memory cell reliability improvement | Hiroyuki Kinoshita, Angela T. Hui, Kuo-Tung Chang, Minh Van Ngo, Hiroyuki Ogawa | 2014-02-25 |
| 8614475 | Void free interlayer dielectric | Minh Van Ngo, Hirokazu Tokuno, Angela T. Hui, Wenmei Li | 2013-12-24 |
| 8536011 | Junction leakage suppression in memory devices | Shibly S. Ahmed, Jun-Kyu Kang, Imran Khan, Dong-Hyuk Ju, Chuan Lin | 2013-09-17 |
| 8503257 | Read disturb scorecard | Daniel J. Post | 2013-08-06 |
| 8370603 | Architecture for address mapping of managed non-volatile memory | Tahoma M. Toelkes, Nir Jacob Wakrat, Kenneth Louis Herman, Barry Corlett, Vadim Khmelnitsky +2 more | 2013-02-05 |
| 8367493 | Void free interlayer dielectric | Minh Van Ngo, Hirokazu Tokuno, Angela T. Hui, Wenmei Li | 2013-02-05 |
| 8319266 | Etch stop layer for memory cell reliability improvement | Hiroyuki Kinoshita, Angela T. Hui, Kuo-Tung Chang, Minh Van Ngo, Hiroyuki Ogawa | 2012-11-27 |
| 7939440 | Junction leakage suppression in memory devices | Shibly S. Ahmed, Jun-Kyu Kang, Imran Khan, Dong-Hyuk Ju, Chuan Lin | 2011-05-10 |
| 6808945 | Method and system for testing tunnel oxide on a memory-related structure | Zhigang Wang, Nian Yang | 2004-10-26 |
| 6716710 | Using a first liner layer as a spacer in a semiconductor device | Nian Yang, Zhigang Wang | 2004-04-06 |
| 6696331 | Method of protecting a stacked gate structure during fabrication | Nian Yang, Zhigang Wang | 2004-02-24 |
| 6689666 | Replacing a first liner layer with a thicker oxide layer when forming a semiconductor device | Nian Yang, Zhigang Wang | 2004-02-10 |
| 6670227 | Method for fabricating devices in core and periphery semiconductor regions using dual spacers | Kei-Leong Ho | 2003-12-30 |
| 6461905 | Dummy gate process to reduce the Vss resistance of flash products | Zhigang Wang, Nian Yang | 2002-10-08 |