Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9285778 | Time to digital converter with successive approximation architecture | Anthony Caviglia, Eric Naviasky | 2016-03-15 |
| 8957802 | Metastability error detection and correction system and method for successive approximation analog-to-digital converters | — | 2015-02-17 |
| 8902093 | Parallel analog to digital converter architecture with charge redistribution and method thereof | Adrian Luigi Leuciuc | 2014-12-02 |
| 8810301 | System and method for level shifting signals with adjustably controlled frequency response | Michael Casas | 2014-08-19 |
| 8344925 | System and method for adaptive timing control of successive approximation analog-to-digital conversion | — | 2013-01-01 |
| 8081024 | CMOS phase interpolation system | — | 2011-12-20 |
| 8036300 | Dual loop clock recovery circuit | Eric Naviasky | 2011-10-11 |
| 7948270 | System and method for level translation in serial data interface | Adrian Luigi Leuciuc | 2011-05-24 |
| 7773013 | Voltage interpolation in digital-to-analog signal conversion | Stephen Williams, Eric Naviasky | 2010-08-10 |
| 7587012 | Dual loop clock recovery circuit | Eric Naviasky | 2009-09-08 |
| 7480358 | CDR-based clock synthesis | Hamid Partovi | 2009-01-20 |
| 7417572 | Voltage interpolation in digital-to-analog signal conversion | Stephen Williams, Eric Naviasky | 2008-08-26 |
| 7127017 | Clock recovery circuit with second order digital filter | C. Thomas Gray, Scott David Huss | 2006-10-24 |
| 6664814 | Output driver for an integrated circuit | Luca Ravezzi, Alberto Baldisserotto | 2003-12-16 |
| 6002279 | Clock recovery circuit | Eric Naviasky, Patrick Farrell, Anthony Caviglia, John Ebner, Hugh Miller Thompson +1 more | 1999-12-14 |
| 5552784 | Distortion reduction circuit for analog to digital converter system | — | 1996-09-03 |
| 5084868 | Common bus multinode sensor system | Thomas F. Kelly, Eric Naviasky, Daniel W. Jefferies, John R. Smith | 1992-01-28 |
| 4903023 | Subranging analog-to-digital converter with digital error correction | Eric Naviasky | 1990-02-20 |
| 4903024 | A/D converter system with error correction and calibration apparatus and method | Thomas K. Lisle, Jr. | 1990-02-20 |
| 4862171 | Architecture for high speed analog to digital converters | — | 1989-08-29 |
| 4770842 | Common bus multinode sensor system | Thomas F. Kelly, Eric Naviasky, Daniel W. Jefferies, John R. Smith | 1988-09-13 |
| 4612533 | Harmonic distortion reduction technique for data acquistion | — | 1986-09-16 |
| 4506171 | Latching type comparator | Robert McCabe, Eric Naviasky | 1985-03-19 |