Issued Patents All Time
Showing 26–50 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5751986 | Computer system with self-consistent ordering mechanism | Michael A. Fetterman, Glenn J. Hinton, Andrew F. Glew, Robert P. Colwell | 1998-05-12 |
| 5729728 | Method and apparatus for predicting, clearing and redirecting unpredicted changes in instruction flow in a microprocessor | Robert P. Colwell, Atiq Bajwa, Michael A. Fetterman, Andrew F. Glew, Glenn J. Hinton | 1998-03-17 |
| 5721855 | Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer | Glenn J. Hinton, Andrew F. Glew, Michael A. Fetterman, Robert P. Colwell | 1998-02-24 |
| 5717882 | Method and apparatus for dispatching and executing a load operation to memory | Jeffrey M. Abramson, Haitham Akkary, Andrew F. Glew, Glenn J. Hinton, Kris G. Konigsfeld +2 more | 1998-02-10 |
| 5706492 | Method and apparatus for implementing a set-associative branch target buffer | Bradley D. Hoyt, Glenn Hinton, Ashwani K. Gupta, Michael A. Fetterman, Subramanian Natarajan +2 more | 1998-01-06 |
| 5687338 | Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor | Darrell D. Boggs, Robert P. Colwell, Michael A. Fetterman, Andrew F. Glew, Ashwani K. Gupta +1 more | 1997-11-11 |
| 5627985 | Speculative and committed resource files in an out-of-order processor | Michael A. Fetterman, Andrew F. Glew, Glenn J. Hinton, Robert P. Colwell | 1997-05-06 |
| 5615385 | Method and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renaming | Michael A. Fetterman, Andrew F. Glew, Glenn J. Hinton, Robert P. Colwell | 1997-03-25 |
| 5606670 | Method and apparatus for signalling a store buffer to output buffered store data for a load operation on an out-of-order execution computer system | Jeffrey M. Abramson, Haitham Akkary, Andrew F. Glew, Glenn J. Hinton, Kris G. Konigsfeld +1 more | 1997-02-25 |
| 5604877 | Method and apparatus for resolving return from subroutine instructions in a computer processor | Bradley D. Hoyt, Glenn J. Hinton, Ashwani K. Gupta, Michael A. Fetterman, Subramanian Natarajan +2 more | 1997-02-18 |
| 5604753 | Method and apparatus for performing error correction on data from an external memory | John M. Bauer, Glenn J. Hinton, Gregory P. Meece | 1997-02-18 |
| 5604878 | Method and apparatus for avoiding writeback conflicts between execution units sharing a common writeback path | Robert P. Colwell, Michael A. Fetterman, Andrew F. Glew, Glenn J. Hinton, Robert W. Martell | 1997-02-18 |
| 5588126 | Methods and apparatus for fordwarding buffered store data on an out-of-order execution computer system | Jeffrey M. Abramson, Haitham Akkary, Andrew F. Glew, Glenn J. Hinton, Kris G. Konigsfeld +1 more | 1996-12-24 |
| 5586278 | Method and apparatus for state recovery following branch misprediction in an out-of-order microprocessor | Glenn J. Hinton | 1996-12-17 |
| 5584037 | Entry allocation in a circular buffer | Andrew F. Glew, Michael A. Fetterman, Glenn J. Hinton, Robert P. Colwell, Steven J. Griffith +2 more | 1996-12-10 |
| 5584038 | Entry allocation in a circular buffer using wrap bits indicating whether a queue of the circular buffer has been traversed | Andrew F. Glew, Michael A. Fetterman, Glenn J. Hinton, Robert P. Colwell, Steven J. Griffith +2 more | 1996-12-10 |
| 5574871 | Method and apparatus for implementing a set-associative branch target buffer | Bradley D. Hoyt, Glenn J. Hinton, Ashwani K. Gupta, Michael A. Fetterman, Subramanian Natarajan +2 more | 1996-11-12 |
| 5574942 | Hybrid execution unit for complex microprocessor | Robert P. Colwell, Michael A. Fetterman, Andrew F. Glew, Glenn J. Hinton, Stephen M. Coward +1 more | 1996-11-12 |
| 5564111 | Method and apparatus for implementing a non-blocking translation lookaside buffer | Andrew F. Glew, Haitham Akkary, Robert P. Colwell, Glenn J. Hinton, Michael A. Fetterman | 1996-10-08 |
| 5564056 | Method and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renaming | Michael A. Fetterman, Andrew F. Glew, Glenn J. Hinton, Robert P. Colwell | 1996-10-08 |
| 5561814 | Methods and apparatus for determining memory operating characteristics for given memory locations via assigned address ranges | Andrew F. Glew, Glenn J. Hinton, Michael A. Fetterman, Robert P. Colwell, Frederick J. Pollack | 1996-10-01 |
| 5555432 | Circuit and method for scheduling instructions by predicting future availability of resources required for execution | Glenn J. Hinton, Robert W. Martell, Michael A. Fetterman, James L. Schwartz | 1996-09-10 |
| 5553256 | Apparatus for pipeline streamlining where resources are immediate or certainly retired | Michael A. Fetterman, Glenn J. Hinton, Robert W. Martell | 1996-09-03 |
| 5546597 | Ready selection of data dependent instructions using multi-cycle cams in a processor performing out-of-order instruction execution | Robert W. Martell, Glenn J. Hinton, Michael A. Fetterman, Robert P. Colwell, Andrew F. Glew | 1996-08-13 |
| 5471633 | Idiom recognizer within a register alias table | Robert P. Colwell, Andrew F. Glew, Glenn J. Hinton, David W. Clift | 1995-11-28 |