JA

Jeffrey M. Abramson

IN Intel: 19 patents #2,136 of 30,777Top 7%
Overall (All Time): #203,908 of 4,157,543Top 5%
21
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11945532 Rotatable carousel storage unit for bicycles Eric L. Rayl, Gavin Brink, Paul De La Port, April JOHNSON 2024-04-02
5898854 Apparatus for indicating an oldest non-retired load operation in an array Kris G. Konigsfeld 1999-04-27
5860154 Method and apparatus for calculating effective memory addresses Haitham Akkary, Andrew F. Glew, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland +1 more 1999-01-12
5784639 Load buffer integrated dynamic decoding logic 1998-07-21
5781790 Method and apparatus for performing floating point to integer transfers and vice versa Kris G. Konigsfeld 1998-07-14
5778220 Method and apparatus for disabling interrupts in a highly pipelined processor Kris G. Konigsfeld, Rohit A. Vidwans 1998-07-07
5751983 Out-of-order processor with a memory subsystem which handles speculatively dispatched load operations David B. Papworth, Haitham Akkary, Andrew F. Glew, Glenn J. Hinton, Kris G. Konigsfeld +1 more 1998-05-12
5748937 Computer system that maintains processor ordering consistency by snooping an external bus for conflicts during out of order execution of memory access instructions Haitham Akkary, Andrew F. Glew, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland 1998-05-05
5721857 Method and apparatus for saving the effective address of floating point memory operations in an out-of-order microprocessor Andrew F. Glew, Kris G. Konigsfeld, Atiq Bajwa, Warren R. Morrow, William C. Alexander 1998-02-24
5717882 Method and apparatus for dispatching and executing a load operation to memory Haitham Akkary, Andrew F. Glew, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland +2 more 1998-02-10
5708843 Method and apparatus for handling code segment violations in a computer system Haitham Akkary, Andrew F. Glew, Glenn J. Hinton, Kris G. Konigsfeld, Rohit A. Vidwans 1998-01-13
5694553 Method and apparatus for determining the dispatch readiness of buffered load operations in a processor Kris G. Konigsfeld 1997-12-02
5680572 Cache memory system having data and tag arrays and multi-purpose buffer assembly with multiple line buffers Haitham Akkary, Andrew F. Glew, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland +2 more 1997-10-21
5671444 Methods and apparatus for caching data in a non-blocking manner using a plurality of fill buffers Haitham Akkary, Andrew F. Glew, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland +2 more 1997-09-23
5664137 Method and apparatus for executing and dispatching store operations in a computer system Haitham Akkary, Atig A. Bajwa, Michael A. Fetterman, Andrew F. Glew, Glenn J. Hinton +4 more 1997-09-02
5635862 High-speed block id encoder circuit using dynamic logic Bryon Conley, Borislav Agapiev 1997-06-03
5606670 Method and apparatus for signalling a store buffer to output buffered store data for a load operation on an out-of-order execution computer system Haitham Akkary, Andrew F. Glew, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland +1 more 1997-02-25
5588126 Methods and apparatus for fordwarding buffered store data on an out-of-order execution computer system Haitham Akkary, Andrew F. Glew, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland +1 more 1996-12-24
5577200 Method and apparatus for loading and storing misaligned data on an out-of-order execution computer system Haitham Akkary, Andrew F. Glew, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland 1996-11-19
5434987 Method and apparatus for preventing incorrect fetching of an instruction of a self-modifying code sequence with dependency on a bufered store Haitham Akkary, Andrew F. Glew, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland 1995-07-18
5420991 Apparatus and method for maintaining processing consistency in a computer system having multiple processors Kris G. Konigsfeld, Haitham Akkary, Glenn J. Hinton, Andrew F. Glew 1995-05-30