Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7159154 | Technique for synchronizing faults in a processor having a replay system | Yung-Hsiang Lee, Douglas M. Carmean | 2007-01-02 |
| 6643742 | Method and system for efficient cache memory updating with a least recently used (LRU) protocol | James A. Beavens | 2003-11-04 |
| 6629271 | Technique for synchronizing faults in a processor having a replay system | Yung-Hsiang Lee, Douglas M. Carmean | 2003-09-30 |
| 5889982 | Method and apparatus for generating event handler vectors based on both operating mode and event type | Scott Dion Rodgers, Joel Huang, Michael A. Fetterman, Kamla P. Huck | 1999-03-30 |
| 5826069 | Having write merge and data override capability for a superscalar processing device | Wesley McCullough | 1998-10-20 |
| 5778220 | Method and apparatus for disabling interrupts in a highly pipelined processor | Jeffrey M. Abramson, Kris G. Konigsfeld | 1998-07-07 |
| 5777928 | Multi-port register | Wesley McCullough, Joel Huang, Joseph Rohlman | 1998-07-07 |
| 5740393 | Instruction pointer limits in processor that performs speculative out-of-order instruction execution | Darrell D. Boggs, Michael A. Fetterman, Andrew F. Glew | 1998-04-14 |
| 5708843 | Method and apparatus for handling code segment violations in a computer system | Jeffrey M. Abramson, Haitham Akkary, Andrew F. Glew, Glenn J. Hinton, Kris G. Konigsfeld | 1998-01-13 |
| 5574935 | Superscalar processor with a multi-port reorder buffer | Wesley McCullough, Joel Huang, Joseph Rohlman | 1996-11-12 |
| 5463745 | Methods and apparatus for determining the next instruction pointer in an out-of-order execution computer system | Darrell D. Boggs, Michael A. Fetterman, Andrew F. Glew | 1995-10-31 |