Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12380005 | Failover for pooled memory | Thomas Willhalm, Francesc Guim Bernat, Karthik Kumar, Rita Deepak Gupta, Mark A. Schmisseur | 2025-08-05 |
| 12340863 | Stacked memory chip solution with reduced package inputs/outputs (I/Os) | Chong J. Zhao, Shigeki Tomishima, Kuljit S. Bains, James A. McCall | 2025-06-24 |
| 12282366 | System, apparatus and methods for power communications according to a CXL power protocol | Francesc Guim Bernat, Karthik Kumar, Alexander Bachmutsky, Rita Deepak Gupta | 2025-04-22 |
| 11245604 | Techniques to support multiple interconnect protocols for a common set of interconnect connectors | Mahesh Wagh, Mark S. Myers, Stephen R. Van Doren, Bassam N. Coury | 2022-02-08 |
| 11036642 | Architectural enhancements for computing systems having artificial intelligence logic disposed locally to memory | Francesc Guim Bernat, Mark A. Schmisseur, Kshitij A. Doshi, Kimberly A. Malone | 2021-06-15 |
| 10884195 | Techniques to support multiple interconnect protocols for a common set of interconnect connectors | Mahesh Wagh, Mark S. Myers, Stephen R. Van Doren, Bassam N. Coury | 2021-01-05 |
| 10719443 | Apparatus and method for implementing a multi-level memory hierarchy | Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad +5 more | 2020-07-21 |
| 10586764 | Semiconductor package with programmable signal routing | Russell S. Aoki | 2020-03-10 |
| 10581596 | Technologies for managing errors in a remotely accessible memory pool | Mark A. Schmisseur, Murugasamy K. Nachimuthu | 2020-03-03 |
| 10476670 | Technologies for providing remote access to a shared memory pool | Mark A. Schmisseur, Murugasamy K. Nachimuthu | 2019-11-12 |
| 10469252 | Technologies for efficiently managing allocation of memory in a shared memory pool | Mark A. Schmisseur, Murugasamy K. Nachimuthu | 2019-11-05 |
| 10331614 | Method and apparatus for server platform architectures that enable serviceable nonvolatile memory modules | Bassam N. Coury, Mohan J. Kumar, Murugasamy K. Nachimuthu, Thi Dang, Russell J. Wunderlich | 2019-06-25 |
| 10241912 | Apparatus and method for implementing a multi-level memory hierarchy | Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad +5 more | 2019-03-26 |
| 10211120 | Rework grid array interposer with direct power | Russell S. Aoki, Jonathan W. Thibado, Jeffory L. Smalley, David J. Llapitan, Thomas A. Boyd +2 more | 2019-02-19 |
| 10176108 | Accessing memory coupled to a target node from an initiator node | Murugasamy K. Nachimuthu, Mohan J. Kumar | 2019-01-08 |
| 10146657 | Initialization trace of a computing device | Robert C. Swanson, C. Brendan S. Traw, Vincent J. Zimmer, Mallik Bulusu, John R. Lindsley +8 more | 2018-12-04 |
| 9832876 | CPU package substrates with removable memory mechanical interfaces | Mani N. Prakash, Thomas T. Holden, Jeffory L. Smalley, Ram Viswanath, Bassam N. Coury +11 more | 2017-11-28 |
| 9600416 | Apparatus and method for implementing a multi-level memory hierarchy | Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad +5 more | 2017-03-21 |
| 9507534 | Home agent multi-level NVM memory architecture | Zhong-Ning Cai | 2016-11-29 |
| 9378133 | Autonomous initialization of non-volatile random access memory in a computer system | Murugasamy K. Nachimuthu, Mohan J. Kumar | 2016-06-28 |
| 9361257 | Mechanism for facilitating customization of multipurpose interconnect agents at computing devices | Zhong-Ning Cai | 2016-06-07 |
| 9317429 | Apparatus and method for implementing a multi-level memory hierarchy over common memory channels | Raj K. Ramanujan, David J. Zimmerman, Mohan J. Kumar, Muthukumar P. Swaminathan, Bassam N. Coury | 2016-04-19 |
| 9256493 | Memory module architecture | Murugasamy K. Nachimuthu, Mohan J. Kumar, Debaleena Das | 2016-02-09 |
| 9015388 | Controlling access to storage in a computing device | Murugasamy K. Nachimuthu, Mohan J. Kumar | 2015-04-21 |