Issued Patents All Time
Showing 25 most recent of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11507430 | Accelerated resource allocation techniques | Rasika Subramanian, Francesc Guim Bernat | 2022-11-22 |
| 11238203 | Systems and methods for accessing storage-as-memory | Rameshkumar G. Illikkal, Ananth Sankaranarayanan, Pratik M. Marolia, Suchit Subhaschandra, Dave B. Minturn | 2022-02-01 |
| 11200176 | Dynamic partial power down of memory-side cache in a 2-level memory hierarchy | Raj K. Ramanujan, Glenn J. Hinton | 2021-12-14 |
| 10795823 | Dynamic partial power down of memory-side cache in a 2-level memory hierarchy | Raj K. Ramanujan, Glenn J. Hinton | 2020-10-06 |
| 10719443 | Apparatus and method for implementing a multi-level memory hierarchy | Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad +5 more | 2020-07-21 |
| 10541009 | Write data mask for power reduction | Robert M. Ellis, Rajesh Sundaram | 2020-01-21 |
| 10504591 | Adaptive configuration of non-volatile memory | Shekoufeh Qawami, Rajesh Sundaram, Blaise Fanning | 2019-12-10 |
| 10347354 | Boundary scan chain for stacked memory | — | 2019-07-09 |
| 10241912 | Apparatus and method for implementing a multi-level memory hierarchy | Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad +5 more | 2019-03-26 |
| 10224115 | Self-repair logic for stacked memory architecture | Joon-Sung Yang, Darshan Kobla, Liwei Ju | 2019-03-05 |
| 10025737 | Interface for storage device access over memory bus | Shekoufeh Qawami, Rajesh Sundaram, Robert W. Faber | 2018-07-17 |
| 10026475 | Adaptive configuration of non-volatile memory | Shekoufeh Qawami, Rajesh Sundaram, Blaise Fanning | 2018-07-17 |
| 9922725 | Integrated circuit defect detection and repair | Bruce Querbach, William K. Lui, David G. Ellis, Theodore Z. Schoenborn, Christopher W. Hampson +2 more | 2018-03-20 |
| 9646720 | Self-repair logic for stacked memory architecture | Joon-Sung Yang, Darshan Kobla, Liwei Ju | 2017-05-09 |
| 9600416 | Apparatus and method for implementing a multi-level memory hierarchy | Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad +5 more | 2017-03-21 |
| 9564245 | Integrated circuit defect detection and repair | Bruce Querbach, Theodore Z. Schoenborn, David G. Ellis, Christopher W. Hampson, Ifar Wan +3 more | 2017-02-07 |
| 9548137 | Integrated circuit defect detection and repair | Bruce Querbach, William K. Lui, David G. Ellis, Theodore Z. Schoenborn, Christopher W. Hampson +2 more | 2017-01-17 |
| 9476940 | Boundary scan chain for stacked memory | — | 2016-10-25 |
| 9418700 | Bad block management mechanism | Raj K. Ramanujan, Glenn J. Hinton | 2016-08-16 |
| 9317429 | Apparatus and method for implementing a multi-level memory hierarchy over common memory channels | Raj K. Ramanujan, Dimitrios Ziakas, Mohan J. Kumar, Muthukumar P. Swaminathan, Bassam N. Coury | 2016-04-19 |
| 9298573 | Built-in self-test for stacked memory architecture | Darshan Kobla, Vimal Natarajan | 2016-03-29 |
| 9236143 | Generic address scrambler for memory circuit test engine | Darshan Kobla, Vimal Natarajan | 2016-01-12 |
| 9195589 | Adaptive configuration of non-volatile memory | Shekoufeh Qawami, Rajesh Sundaram, Blaise Fanning | 2015-11-24 |
| 9190173 | Generic data scrambler for memory circuit test engine | Darshan Kobla, John C. Johnson, Vimal Natarajan | 2015-11-17 |
| 9158616 | Method and system for error management in a memory device | Kuljit S. Bains, Dennis W. Brzezinski, Michael W. Williams, John B. Halbert | 2015-10-13 |