Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11119838 | Techniques for handling errors in persistent memory | Mohan J. Kumar, Murugasamy K. Nachimuthu | 2021-09-14 |
| 10915254 | Technologies for contemporaneous access of non-volatile and volatile memory in a memory device | Kunal A. Khochare, Richard P. Mangold, Shachi K. Thakkar | 2021-02-09 |
| 10719443 | Apparatus and method for implementing a multi-level memory hierarchy | Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, David J. Zimmerman +5 more | 2020-07-21 |
| 10417070 | Techniques for handling errors in persistent memory | Mohan J. Kumar, Murugasamy K. Nachimuthu | 2019-09-17 |
| 10296238 | Technologies for contemporaneous access of non-volatile and volatile memory in a memory device | Kunal A. Khochare, Richard P. Mangold, Shachi K. Thakkar | 2019-05-21 |
| 10241912 | Apparatus and method for implementing a multi-level memory hierarchy | Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, David J. Zimmerman +5 more | 2019-03-26 |
| 9817738 | Clearing poison status on read accesses to volatile memory regions allocated in non-volatile memory | Raj K. Ramanujan, Richard P. Mangold, Theodros Yigzaw | 2017-11-14 |
| 9753793 | Techniques for handling errors in persistent memory | Mohan J. Kumar, Murugasamy K. Nachimuthu | 2017-09-05 |
| 9600416 | Apparatus and method for implementing a multi-level memory hierarchy | Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, David J. Zimmerman +5 more | 2017-03-21 |