Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Apparatus and method for implementing a multi-level memory hierarchy

Apparatus and method for implementing a multi-level memory hierarchy

US Patent 9600416 · Granted Mar 21, 2017

Estimated economic value: $8,001,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

On-package die-to-die (D2D) interconnect for memory using universal chiplet inte2025
Supporting mixed read in non-volatile memory controller2025
Bypass buffer for worn out codewords2025
Memory access tracing2025
Method to minimize hot/cold page detection overhead on running workloads2025
System and methods for real time raman spectroscopy for cancer detection2025
Dynamic multilevel memory system2025
Sharing memory and I/O services between nodes2025
Selective fill for logical control over hardware multilevel memory2025
Failover for pooled memory2025
Direct memory access (DMA) engine with network interface capabilities2025
Distribution of error checking and correction (ECC) bits to allocate ECC bits fo2025