| 12321898 |
System and method for generating skill-centric online resumes with verifiable skills |
— |
2025-06-03 |
|
| 11210637 |
System and method for generating skill-centric online resumes with verifiable skills |
— |
2021-12-28 |
|
| 10579464 |
Method and apparatus for partial cache line sparing |
Rajat Agarwal, Brian S. Morris |
2020-03-03 |
$18,388,000 |
| 10552643 |
Fast boot up memory controller |
John V. Lovelace, Sreenivas Mandava |
2020-02-04 |
$21,361,000 |
| 10496473 |
Extracting selective information from on-die dynamic random access memory (DRAM) error correction code (ECC) |
Bill Nale, Kuljit S. Bains, John B. Halbert |
2019-12-03 |
$19,496,000 |
| 9910728 |
Method and apparatus for partial cache line sparing |
Rajat Agarwal, Brian S. Morris |
2018-03-06 |
$18,859,000 |
| 9904591 |
Device, system and method to restrict access to data error information |
John B. Halbert, Kuljit S. Bains, Bill Nale |
2018-02-27 |
$23,267,000 |
| 9811420 |
Extracting selective information from on-die dynamic random access memory (DRAM) error correction code (ECC) |
Bill Nale, Kuljit S. Bains, John B. Halbert |
2017-11-07 |
$13,901,000 |
| 9760435 |
Apparatus and method for generating common locator bits to locate a device or column error during error correction operations |
— |
2017-09-12 |
$10,213,000 |
| 9697094 |
Dynamically changing lockstep configuration |
George H. Huang, Jing Ling, Reza E. Daftari, Meera Ganesan |
2017-07-04 |
|
| 9691505 |
Dynamic application of error correction code (ECC) based on error type |
Rajat Agarwal |
2017-06-27 |
$7,334,000 |
| 9613722 |
Method and apparatus for reverse memory sparing |
George H. Huang, Brian S. Morris, Rajat Agarwal |
2017-04-04 |
$8,141,000 |
| 9391637 |
Error correcting code scheme utilizing reserved space |
Rajat Agrawal, Kai Cheng |
2016-07-12 |
$10,128,000 |
| 9256493 |
Memory module architecture |
Murugasamy K. Nachimuthu, Mohan J. Kumar, Dimitrios Ziakas |
2016-02-09 |
$15,927,000 |
| 9195551 |
Enhanced storage of metadata utilizing improved error detection and correction in computer memory |
Rajat Agarwal, C. Scott Huddleston |
2015-11-24 |
$18,043,000 |
| 8914704 |
Mechanism for achieving high memory reliablity, availability and serviceability |
Kai Cheng, Jonathan C. Jasper |
2014-12-16 |
$19,599,000 |
| 8745464 |
Rank-specific cyclic redundancy check |
Ramesh Subashchandrabose, Tessil Thomas, Sambaran Mitra, Kai Cheng |
2014-06-03 |
$12,928,000 |
| 8527836 |
Rank-specific cyclic redundancy check |
Ramesh Subashchandrabose, Tessil Thomas, Sambaran Mitra, Kai Cheng |
2013-09-03 |
$32,940,000 |
| 7930602 |
Method and system for performing a double pass NTH fail bitmap of a device memory |
— |
2011-04-19 |
$7,054,000 |
| 7530008 |
Scalable-chip-correct ECC scheme |
Alan H. Mandel |
2009-05-05 |
$16,300,000 |
| 6802036 |
High-speed first-in-first-out buffer |
Kenneth Chiu, Jurgen Schulz, Daniel F. McMahon |
2004-10-05 |
$18,736,000 |
