EM

Enric Musoll

MT Mips Technologies: 8 patents #22 of 129Top 20%
XP Xpliant: 5 patents #2 of 12Top 20%
CL Cavium, Llc.: 1 patents #141 of 220Top 65%
Disney: 1 patents #3,944 of 6,686Top 60%
📍 San Jose, CA: #4,326 of 32,062 inventorsTop 15%
🗺 California: #40,325 of 386,348 inventorsTop 15%
Overall (All Time): #314,678 of 4,157,543Top 8%
15
Patents All Time

Issued Patents All Time

Showing 1–15 of 15 patents

Patent #TitleCo-InventorsDate
11621923 Queueing system with head-of-line block avoidance Avinash Sodani, Dan Tu, Chia-Hsin Chen 2023-04-04
9736069 Method for storing and retrieving packets in high bandwidth and low latency packet processing devices Tsahi Daniel, Dan Tu 2017-08-15
9509585 Apparatus and method for time stamping packets across several nodes in a network Tsahi Daniel, Sridevi Polasanapalli 2016-11-29
9438539 Apparatus and method for optimizing the number of accesses to page-reference count storage in page link list based switches Tsahi Daniel, Sridevi Polasanapalli 2016-09-06
9262369 Apparatus and method for accelerated page link list processing in a packet processor operating at wirespeed Tsahi Daniel, Dan Tu, Sridevi Polasanapalli 2016-02-16
9256380 Apparatus and method for packet memory datapath processing in high bandwidth packet processing devices Tsahi Daniel, Dan Tu 2016-02-09
9009364 Apparatus and method for accelerated page link list processing in a packet processor operating at wirespeed Tsahi Daniel, Dan Tu, Sridevi Polasanapalli 2015-04-14
7715410 Queueing system for processors in packet routing operations Mario Nemirovsky, Stephen Melvin, Narendra Sankar, Nandakumar Sampath, Adolfo Nemirovsky 2010-05-11
7661112 Methods and apparatus for managing a buffer of events in the background Mario Nemirovsky, Narendra Sankar, Adolfo Nemirovsky 2010-02-09
7551626 Queueing system for processors in packet routing operations Mario Nemirovsky, Stephen Melvin, Narendra Sankar, Nandakumar Sampath, Adolfo Nemirovsky 2009-06-23
7502876 Background memory manager that determines if data structures fits in memory with memory state transactions map Mario Nemirovsky, Narendra Sankar, Adolfo Nemirovsky 2009-03-10
7237093 Instruction fetching system in a multithreaded processor utilizing cache miss predictions to fetch instructions from multiple hardware streams Mario Nemirovsky 2007-06-26
7058064 Queueing system for processors in packet routing operations Mario Nemirovsky, Stephen Melvin, Narendra Sankar, Nandakumar Sampath, Adolfo Nemirovsky 2006-06-06
7035997 Methods and apparatus for improving fetching and dispatch of instructions in multithreaded processors Mario Nemirovsky 2006-04-25
7032226 Methods and apparatus for managing a buffer of events in the background Mario Nemirovsky, Narendra Sankar, Adolfo Nemirovsky 2006-04-18