Issued Patents All Time
Showing 51–75 of 75 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9720827 | Providing multiple memory modes for a processor including internal memory | Robert J. Kyanko, Richard J. Greco, Andreas Kleen, Milind B. Girkar, Christopher M. Cantalupo | 2017-08-01 |
| 9594648 | Controlling non-redundant execution in a redundant multithreading (RMT) processor | Glenn J. Hinton, Steven Raasch, Sebastien Hily, John G. Holm, Ronak Singhal +1 more | 2017-03-14 |
| 9524191 | Apparatus including a stall counter to bias processing element selection, and masks to allocate reservation unit entries to one or more processing elements | Morris Marden, Matthew C. Merten, Alexandre J. Farcy, James Hadley, Ilhyun Kim | 2016-12-20 |
| 9507596 | Instruction and logic for prefetcher throttling based on counts of memory accesses to data sources | Ashok Jagannathan, Prabhat Jain, Krishna N. Vinod | 2016-11-29 |
| 9081688 | Obtaining data for redundant multithreading (RMT) execution | Glenn J. Hinton, Steven Raasch, Sebastien Hily, John G. Holm, Ronak Singhal +4 more | 2015-07-14 |
| 8825989 | Technique to perform three-source operations | Stephan Jourdan, Alexandre J. Farcy, Per Hammarlund | 2014-09-02 |
| 8793689 | Redundant multithreading processor | Glenn J. Hinton, Steven Raasch, Sebastien Hily, John G. Holm, Ronak Singhal +1 more | 2014-07-29 |
| 8589663 | Technique to perform three-source operations | Stephan Jourdan, Alexandre J. Farcy, Per Hammarlund | 2013-11-19 |
| 8521993 | Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessor | Morris Marden, Matthew C. Merten, Alexandre J. Farcy, James Hadley, Ilhyun Kim | 2013-08-27 |
| 8504804 | Managing multiple threads in a single pipeline | Matthew C. Merten, James Hadley, Alexandre J. Farcy, Iredamola Olopade | 2013-08-06 |
| 8438369 | Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessor | Morris Marden, Matthew C. Merten, Alexandre J. Farcy, James Hadley, Ilhyun Kim | 2013-05-07 |
| 8402253 | Managing multiple threads in a single pipeline | Matthew C. Merten, James Hadley, Alexandre J. Farcy, Iredamola Olopade | 2013-03-19 |
| 7721076 | Tracking an oldest processor event using information stored in a register and queue entry | Vijaykumar B. Kadgi, Zeev Sperber | 2010-05-18 |
| 7711898 | Register alias table cache to map a logical register to a physical register | Stephan Jourdan, Samie B. Samaan | 2010-05-04 |
| 7600103 | Speculatively scheduling micro-operations after allocation | Rahul Kulkarni, David K. Li | 2009-10-06 |
| 7562206 | Multilevel scheme for dynamically and statically predicting instruction resource utilization to generate execution cluster partitions | Alexandre J. Farcy, Stephan Jourdan, Per Hammarlund, Mark Charles Davis | 2009-07-14 |
| 7529913 | Late allocation of registers | Per Hammarlund, Stephan Jourdan | 2009-05-05 |
| 7502912 | Method and apparatus for rescheduling operations in a processor | Per Hammarlund, Stephan Jourdan | 2009-03-10 |
| 7475225 | Method and apparatus for microarchitecture partitioning of execution clusters | Stephan Jourdan, Alexandre J. Farcy, Per Hammarlund, Sebastien Hily, Mark Charles Davis | 2009-01-06 |
| 7457938 | Staggered execution stack for vector processing | Stephan Jourdan, Michael A. Fetterman, Per Hammarlund, Ronak Singhal, Glenn J. Hinton | 2008-11-25 |
| 7404065 | Flow optimization and prediction for VSSE memory operations | Stephan Jourdan, Per Hammarlund, Michael A. Fetterman, Michael Cornaby, Glenn J. Hinton | 2008-07-22 |
| 7363430 | Determination of cache entry for future operation | Samie B. Samaan | 2008-04-22 |
| 7272701 | Method and apparatus for limiting ports in a register alias table having high-bandwidth and low-bandwidth structures | — | 2007-09-18 |
| 7174428 | Method and system for transforming memory location references in instructions | Sebastien Hily, Per Hammarlund | 2007-02-06 |
| 5845103 | Computer with dynamic instruction reuse | Gurindar S. Sohi | 1998-12-01 |